气相二氧化硅生产现状及其在涂料中的应用

介绍了气相二氧化硅国内外生产状况,根据气相二氧化硅在涂料方面的应用特点及主 要技术关键的分析,提出了建议。     

Broad-band MMICs based on modified loss-compensation method using 0.35-/spl mu/m SiGe BiCMOS technology

Using the concept of loss compensation, novel broad-band monolithic microwave integrated circuits (MMICs), including an amplifier and an analog multiplier/mixer, with LC ladder matching networks in a commercial 0.35-mum SiGe BiCMOS technology are demonstrated for the first time. An HBT two-stage cascade single-stage distributed amplifier (2-CSSDA) using the modified loss-compensation technique is presented. It demonstrates a small-signal gain of better than 15 dB from dc to 28 GHz (gain-bandwidth product=157 GHz) with a low power consumption of 48 mW and a miniature chip size of 0.63 mm² including testing pads. The gain-bandwidth product of the modified loss-compensated CSSDA is improved approximately 68% compared with the conventional attenuation-compensation technique. The wide-band amplifier achieves a high gain-bandwidth product with the lowest power consumption and smallest chip size. The broad-band mixer designed using a Gilbert cell with the modified loss-compensation technique achieves a measured power conversion gain of 19 dB with a 3-dB bandwidth from 0.1 to 23 GHz, which is the highest gain-bandwidth product of operation among previously reported MMIC mixers. As an analog multiplier, the measured sensitivity is better than 3000 V/W from 0.1 to 25 GHz, and the measured low-frequency noise floor and corner frequency can be estimated to be 20 nV/sqrt(Hz) and 1.2 kHz, respectively. The mixer performance represents state-of-the-art result of the MMIC broad-band mixers using commercial silicon-based technologies     

Fabrication of Dicing-Free Vertical-Structured High-Power GaN-Based Light-Emitting Diodes With Selective Nickel Electroplating and Patterned Laser Liftoff Techniques

Through the use of selective nickel (Ni) electroplating, patterned laser liftoff technique, and surface roughing of the top n-GaN epilayer, a novel process for the fabrication of vertical-structured metal-substrate GaN-based light-emitting diodes (VM-LEDs) to avoid difficulties in Ni substrate dicing and improve device yield was proposed and demonstrated. In conjunction with a sidewall passivation with SiO₂ and keeping the size of epilayer smaller than that of Ni island, a considerable improvement in yield and device performance were shown. As compared to conventional lateral-structured GaN-based LEDs, VM-LEDs show an increase in light output power about 174% at 350 mA with a significant decrease in forward voltage from 3.5 to 3.17 V     

Interferometric method for preventing mode-hopping in tunable external-cavity semiconductor lasers

A problem in frequency-tuning of external-cavity lasers is mode-hopping between neighbouring external-cavity modes. We demonstrate a new interferometric method for monitoring mode-hoping and an automatic control circuit for a 1.3 ?m grating external-cavity laser that maintains single-mode operation when the lasing frequency is tuned.     

Genetic synthesis of a fuzzy pulse discriminator in electrical discharge machining

In this paper, a sensor system, called a fuzzy pulse discriminator, is developed to classify various discharge pulses in electrical discharge machining (EDM). The fuzzy rules of the pulse discriminator are obtained based on the features of the gap voltage and gap current between the tool workpiece. The membership functions of the fuzzy pulse discriminator are automatically synthesized by using genetic algorithms. The effectiveness of this approach is verified under different cutting parameters.     

Cost Effective VLSI Architectures for Full-Search Block-Matching Motion Estimation Algorithm

In this paper, we present efficient VLSI architectures for full-search block-matching motion estimation (BMME) algorithm. Given a search range, we partition it into sub-search arrays called tiles. By fully exploiting data dependency within a tile, efficient VLSI architectures can be obtained. Using the proposed VLSI architectures, all the block-matchings in a tile can be processed in parallel. All the tiles within a search range can be processed serially or concurrently depending on various requirements. With the consideration of processing speed, hardware cost, and I/O bandwidth, the optimal tile size for a specific video application is analyzed. By partitioning a search range into tiles with appropriate size, flexible VLSI designs with different throughput can be obtained. In this way, cost effective VLSI designs for a wide range of video applications, from H.261 to HDTV, can be achieved.     

A parallel technique for signal-level perceptual organization

Due to the potential for essentially unbounded scene complexity, it is often necessary to translate the sensor-derived signals into richer symbolic representations. A key initial stage in this abstraction process is signal-level perceptual organization (SLPO) involving the processes of partitioning and identification. A parallel SLPO algorithm that follows the global hypothesis testing paradigm, but breaks the iterative structure of conventional region growing through the use of α-partitioning and region filtering is presented. These two techniques segment an image such that the gray-level variation within each region can be described by a regression model. Experimental results demonstrate the effectiveness of this algorithm     

Analysis of ATSC field test results in Taiwan

Field tests of the transmission performance of the ATSC DTV system have been conducted in Taiwan. The test results as well as comparisons against the NTSC system performance are reported and analyzed. From the measured results the reception characteristics of the DTV can be deduced and can provide guidelines for television stations to design the transmission system, schedule equipment deployment, plan service coverage areas, and improve the reception quality of the digital signal     

A broadband PHEMT MMIC distributed doubler using high-pass drain line topology

A broadband frequency doubler, based on distributed amplifier techniques, has been designed to operate from 11 to 21 GHz. In order to reject the fundamental signal over a broadband frequency range, the conventional low-pass drain line structure was replaced with the high-pass structure. This topology can suppress fundamental signals over broadband without any balanced structure so that the chip size can be more compact. Measured conversion losses of better than 10 dB from 11 to 21 GHz input frequencies are achieved with fundamental signal rejection better than 12 dB. To the best of our knowledge, this is the first demonstration of distributed doubler using the high-pass drain line topology.