Parallel Lagrange interpolation on <Emphasis Type="Italic">k</Emphasis>-ary <Emphasis Type="Italic">n</Emphasis>-cubes with maximum channel utilization

This paper proposes an efficient parallel algorithm for computing Lagrange interpolation on k-ary n-cube networks. This is done using the fact that a k-ary n-cube can be decomposed into n link-disjoint Hamiltonian cycles. Using these n link-disjoint cycles, we interpolate Lagrange polynomial using full bandwidth of the employed network. Communication in the main phase of the algorithm is based on an all-to-all broadcast algorithm on the n link-disjoint Hamiltonian cycles exploiting all network channels, and thus, resulting in high-efficiency in using network resources. A performance evaluation of the proposed algorithm reveals an optimum speedup for a typical range of system parameters used in current state-of-the-art implementations.

An ant colony optimization algorithm for the bi-objective shortest path problem

Multi-objective shortest path problem (MOSP) is an extension of a traditional single objective shortest path problem that seeks for the efficient paths satisfying several conflicting objectives between two nodes of a network. MOSP is one of the most important problems in network optimization with wide applications in telecommunication industries, transportation and project management. This research presents an algorithm based on multi-objective ant colony optimization (ACO) to solve the bi-objective shortest path problem. To analyze the efficiency of the algorithm and check for the quality of solutions, experimental analyses are conducted. Two sets of small and large sized problems that generated randomly are solved. Results on the set problems are compared with those of label correcting solutions that is the most known efficient algorithm for solving MOSP. To compare the Pareto optimal frontiers produced by the suggested ACO algorithm and the label correcting algorithm, some performance measures are employed that consider and compare the distance, uniformity distribution and extension of the Pareto frontiers. The results on the set of instance problems show that the suggested algorithm produces good quality non-dominated solutions and time saving in computation of large-scale bi-objective shortest path problems.     

Ultra-area-efficient reversible multiplier

One of the most promising technologies in designing low-power circuits is reversible computing. It is used in nanotechnology, quantum computing, quantum dot cellular automata (QCA), DNA computing, optical computing and in CMOS low-power designs. Because of this broad range of applications, extensive works have been proposed in constructing reversible gates and reversible circuits, including basic universal logic gates, adders and multipliers.In this paper we have highlighted the design of reversible multipliers and have presented two designs. Integration of adder circuit and multiplier in the design is described, in order to utilize the unused capacity of the multipliers.We have achieved reduction in quantum cost compared to similar designs as well as appending the adder circuit to the multiplier which leads to better usage of resources. Additionally, we have described the multiplier problem for implementing n×n reversible multiplier and analyzed the required resources in terms of n. Practical implementation of this design can be achieved with the existing technologies in CMOS and nanotechnology.Lastly, we make a tradeoff between area and time complexity to obtain two designs which can be used in different situations where different requirements are of different importances. We compare the proposed designs with each other and also to the existing ones.     

Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic

Differential Cascode Voltage Switch (DCVS) is a well-known logic style, which constructs robust and reliable circuits. Two main strategies are studied in this paper to form static DCVS-based standard ternary fundamental logic components in digital electronics. While one of the strategies leads to fewer transistors, the other one has higher noise margin. New designs are simulated with HSPICE and 32 nm CNTFET technology at various realistic conditions such as different power supplies, load capacitors, frequencies, and temperatures. Simulations results demonstrate their robustness and efficiency even in the presence of PVT variations. In addition, new noise injection circuits for ternary logic are also presented to perform noise immunity analysis.     

High-Performance Mixed-Mode Universal Min-Max Circuits for Nanotechnology

In this paper a low-power, high-speed and high-resolution voltage-mode Min-Max circuit, as well as a new efficient universal structure for determining the minimum and maximum values of the input digital signals, is proposed for nanotechnology. In addition, the proposed designs provide rail-to-rail input and output signals which enhance the performance and the robustness of the circuits. The advantage of the proposed Min-Max circuit is that it is extendable for any arbitrary n-digit and radix-r input numbers. Comprehensive simulation results at CMOS and CNFET technologies demonstrate the low-power and high-performance operation as well as insusceptibility to PVT variations of the proposed structure.     

Utility-based adaptive radio resource allocation in OFDM wireless networks with traffic prioritization

In this letter, a joint transmit scheduling and dynamic sub-carrier and power allocation method is proposed to exploit multi-user diversity in downlink packet transmission in an OFDM wireless network with mixed real-time and non-real-time traffic patterns. To balance efficiency and fairness and to satisfy the QoS requirements of real-time users, we utilize a utility-based framework and propose a polynomial-time heuristic algorithm to solve the formulated optimization problem. The distinguishing feature of the proposed method is that it gives in one shot, the transmission scheduling, the sub-carriers assigned to each user, and the power allocated to each sub-carrier, based on a fair and efficient framework while satisfying the delay requirements of real-time users.     

Two new low-power Full Adders based on majority-not gates

Two novel low-power 1-bit Full Adder cells are proposed in this paper. Both of them are based on majority-not gates, which are designed with new methods in each cell. The first cell is only composed of input capacitors and CMOS inverters, and the second one also takes advantage of a high-performance CMOS bridge circuit. These kinds of designs enjoy low power consumption, a high degree of regularity, and simplicity. Low power consumption is targeted in implementation of our designs. Eight state-of-the-art 1-bit Full Adders and two proposed Full Adders are simulated using 0.18 μm CMOS technology at many supply voltages. Simulation results demonstrate improvement in terms of power consumption and power-delay product (PDP).     

Improved Thermoelectric Performance of Eco‐Friendly β‐FeSi2–SiGe Nanocomposite via Synergistic Hierarchical Structuring,Phase Percolation,and Selective Doping

A β‐FeSi₂–SiGe nanocomposite is synthesized via a react/transform spark plasma sintering technique, in which eutectoid phase transformation, Ge alloying, selective doping, and sintering are completed in a single process, resulting in a greatly reduced process time and thermal budget. Hierarchical structuring of the SiGe secondary phase to achieve coexistence of a percolated network with isolated nanoscale inclusions effectively decouples the thermal and electrical transport. Combined with selective doping that reduces conduction band offsets, the percolation strategy produces overall electron mobilities 30 times higher than those of similar materials produced using typical powder‐processing routes. As a result, a maximum thermoelectric figure of merit ZT of ≈0.7 at 700 °C is achieved in the β‐FeSi₂–SiGe nanocomposite.     

A novel low-power full-adder cell for low voltage

This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the time-consuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster.     

A new quantum-dot cellular automata full-adder

A novel expandable five-input majority gate for quantum-dot cellular automata and a new full-adder cell are presented. Quantum-dot cellular automata (QCA) is an emerging technology and a possible alternative for semiconductor transistor based technologies. A novel QCA majority-logic gate is proposed. This component is suitable for designing QCA circuits. The gate is simple in structure and powerful in terms of implementing digital functions. By applying these kinds of gates, the hardware requirement for a QCA design can be reduced and circuits can be simpler in level, gate counts and clock phases. In order to verify the functionality of the proposed device, some physical proofs are provided. The proper functionality of the FA is checked by means of computer simulations using QCADesigner tool. Both simulation results and physical relations confirm our claims and its usefulness in designing every digital circuit.