Travelling salesman problem tools for microcomputers

The problem of determining minimum total distance to be travelled by a salesman, who is to visit given cities each only once (i.e. the travelling salesman problem) is one of the most studied problems in computational mathematics. Finding an exact solution is not only intractably difficult, but also exceedingly costly. However, we implemented efficient optimal algorithms for both symmetric and asymmetric distance problems. The programs implemented can solve problems up to 180 cities in reasonable computer time.     

Shift-or string matching with super-alphabets

Given a text T[1…n] and a pattern P[1…m] over some alphabet Σ of size σ, we want to find all the (exact) occurrences of P in T. The well-known shift-or algorithm solves this problem in time O(n⌈m/w⌉), where w is the number of bits in machine word, using bit-parallelism. We show how to extend the bit-parallelism in another direction, using super-alphabets. This gives a speed-up by a factor s, where s is the number of characters processed simultaneously. The algorithm is implemented, and we show that it works well in practice too. The result is the fastest known algorithm for exact string matching for short patterns and small alphabets.     

Improved Soft-Output RAKE Receiver for CDMA Mobile Terminals with High Data Rates

In this paper we propose a soft-output RAKE receiver for CDMA mobile terminals using low spreading factor and/or high-order modulation constellations for high data rates. Based on the outputs of theRAKE correlator fingers, the receiver produces symbol or bit metrics for soft decision decoding. The formulation of these metrics is derived analytically taking into account the multipath propagation, interfering users and channel estimation errors. Simulations show thata performance gain is achieved when low spreading factors or high-order modulation constellations are used.     

Metallocene‐based functionalized polyolefins as compatibilizers in polyolefin nanocomposites

This article reports a study of some functionalized polyolefins evaluated as compatibilizers in polyethylene nanocomposites. The functionalized polymers were prepared by direct metallocene‐mediated copolymerizations of ethylene and a functional comonomer. The prepared nanocomposites were evaluated for mechanical and barrier property enhancement. A good combination of mechanical and barrier properties was obtained with the metallocene‐based functionalized polyethylene. The toughness–stiffness balance was better than or comparable to that achieved with conventional functionalized polymers such as maleic anhydride grafted polyethylene. The results also indicated that these metallocene‐based functionalized polyolefins, when used as compatibilizers, could have relatively higher molar masses and lower functionality than those of conventional post‐reactor‐modified compatibilizers, and so the drawbacks associated with the latter could be avoided. Their inherent properties could also further improve the final nanocomposite properties. This was attributed to the more homogeneous nature of metallocene‐catalyzed polymers in comparison with post‐reactor‐modified products. © 2004 Wiley Periodicals, Inc. J Appl Polym Sci 94: 1094–1100, 2004     

Dopamine release during ethanol drinking in AA rats

The dopamine overflow in the nucleus accumbens of rats from the high alcohol drinking AA line was measured by microdialysis before, during, and after one-half hour sessions of cued drinking of ethanol flavored with saccharin and peppermint or, as a control, saccharin-peppermint drinking. The animals had had extensive previous experience with ethanol drinking. Self-administration of the ethanol solution did not raise the dopamine level substantially: there was a small (17%) but significant increase only during the first 10 min after the onset of drinking. Giving the rats a cue for ethanol, which was part of their daily routine drinking regime, did not raise the dopamine level before ethanol was presented to the rats (i.e., during "anticipation"). The results are consistent with our previous studies showing a lack of a large ethanol-induced dopamine response in rats with previous experience of drinking ethanol and with the idea that although dopamine may play some role in alcohol drinking, it is not the central substrate producing the reinforcement from ethanol in AA rats.     

A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations

Signal processors exploiting ASIC acceleration suffer from sky-rocketing manufacturing costs and long design cycles. FPGA-based systems provide a programmable alternative for exploiting computation parallelism, but the flexibility they provide is not as high as in processor-oriented architectures: HDL or C-to-HDL flows still require specific expertise and a hardware knowledge background. On the other hand, the large size of the configuration bitstream and the inherent complexity of FPGA devices make their dynamic reconfiguration not a very viable approach. Coarse-grained reconfigurable architectures (CGRAs) are an appealing solution but they pose implementation problems and tend to be application specific. This paper presents a scalable CGRA which eases the implementation of algorithms on field programmable gate array (FPGA) platforms. This design option is based on two levels of programmability: it takes advantage of performance and reliability provided by state-of-the-art FPGA technology, and at the same time it provides the user with flexibility, performance and ease of reconfiguration typical of standard CGRAs. The basic cell template provides advanced features such as sub-word SIMD integer and floating-point computation capabilities, as well as saturating arithmetic. Multiple reconfiguration contexts and partial run-time reconfiguration capabilities are provided, tackling this way the problem of high reconfiguration overhead typical of FPGAs. Selected instances of the proposed architecture have been implemented on an Altera Stratix II EP2S180 FPGA. On this system, we mapped some common DSP, image processing, 3D graphics and audio compression algorithms in order to validate our approach and to demonstrate its effectiveness by benchmarking the benefits achieved.     

An industry experiment on the effects of test-driven development on external quality and productivity

Existing empirical studies on test-driven development (TDD) report different conclusions about its effects on quality and productivity. Very few of those studies are experiments conducted with software professionals in industry. We aim to analyse the effects of TDD on the external quality of the work done and the productivity of developers in an industrial setting. We conducted an experiment with 24 professionals from three different sites of a software organization. We chose a repeated-measures design, and asked subjects to implement TDD and incremental test last development (ITLD) in two simple tasks and a realistic application close to real-life complexity. To analyse our findings, we applied a repeated-measures general linear model procedure and a linear mixed effects procedure. We did not observe a statistical difference between the quality of the work done by subjects in both treatments. We observed that the subjects are more productive when they implement TDD on a simple task compared to ITLD, but the productivity drops significantly when applying TDD to a complex brownfield task. So, the task complexity significantly obscured the effect of TDD. Further evidence is necessary to conclude whether TDD is better or worse than ITLD in terms of external quality and productivity in an industrial setting. We found that experimental factors such as selection of tasks could dominate the findings in TDD studies.     

A coarse-grain reconfigurable architecture for multimedia applications featuring subword computation capabilities

This paper presents the design and the implementation of a coarse-grain reconfigurable machine used as an accelerator for a programmable RISC core, to speed up the execution of computationally demanding tasks like multimedia applications. We created a VHDL model of the proposed architecture and implemented it on a FPGA board for prototyping purposes; then we mapped on our architecture some DSP and image processing algorithms as a benchmark. In particular, we provided the proposed architecture with subword computation capabilities, which turns out to be extremely effective especially when dealing with image processing algorithms, achieving significant benefits in terms of speed and efficiency in resource usage. To create the configuration bitstream (configware) we created a tool based on a graphical user interface (GUI) which provides a first step towards the automation of the programming flow of our design: the tool is meant to ease the life of the programmer, relieving him from the burden of calculating the configuration bits by hand. Synthesis results indicate that the area occupation and the operating frequency of our design are reasonable also when compared to other similar design. In addition to this, the amount of clock cycles taken by our machine to perform a given algorithm is orders of magnitude smaller than the one required by a corresponding software implementation on a RISC microprocessor.