The use of data-derived label hierarchies in multi-label classification

Instead of traditional (multi-class) learning approaches that assume label independency, multi-label learning approaches must deal with the existing label dependencies and relations. Many approaches try to model these dependencies in the process of learning and integrate them in the final predictive model, without making a clear difference between the learning process and the process of modeling the label dependencies. Also, the label relations incorporated in the learned model are not directly visible and can not be (re)used in conjunction with other learning approaches. In this paper, we investigate the use of label hierarchies in multi-label classification, constructed in a data-driven manner. We first consider flat label sets and construct label hierarchies from the label sets that appear in the annotations of the training data by using a hierarchical clustering approach. The obtained hierarchies are then used in conjunction with hierarchical multi-label classification (HMC) approaches (two local model approaches for HMC, based on SVMs and PCTs, and two global model approaches, based on PCTs for HMC and ensembles thereof). The experimental results reveal that the use of the data-derived label hierarchy can significantly improve the performance of single predictive models in multi-label classification as compared to the use of a flat label set, while this is not preserved for the ensemble models.     

Globally Synchronized Frames for guaranteed quality-of-service in on-chip networks

Future chip multiprocessors (CMPs) may have hundreds to thousands of threads competing to access shared resources, and will require quality-of-service (QoS) support to improve system utilization. This paper introduces Globally-Synchronized Frames (GSF), a framework for providing guaranteed QoS in on-chip networks in terms of minimum bandwidth and maximum delay bound. The GSF framework can be easily integrated in a conventional virtual channel (VC) router without significantly increasing the hardware complexity. We exploit a fast on-chip barrier network to efficiently implement GSF. Performance guarantees are verified by analysis and simulation. According to our simulations, all concurrent flows receive their guaranteed minimum share of bandwidth in compliance with a given bandwidth allocation. The average throughput degradation of GSF on an 8×8 mesh network is within 10% compared to the conventional best-effort VC router.     

Using simulations of reduced precision arithmetic to design a neuro-microprocessor

This article describes some of our recent work in the development of computer architectures for efficient execution of artificial neural network algorithms. Our earlier system, the Ring Array Processor (RAP), was a multiprocessor based on commercial DSPs with a low-latency ring interconnection scheme. We have used the RAP to simulate variable precision arithmetic to guide us in the design of arithmetic units for high performance neurocomputers to be implemented with custom VLSI. The RAP system played a critical role in this study, enabling us to experiment with much larger networks than would otherwise be possible. Our study shows that back-propagation training algorithms only require moderate precision. Specifically, 16b weight values and 8b output values are sufficient to achieve training and classification results comparable to 32b floating point. Although these results were gathered for frame classification in continuous speech, we expect that they will extend to many other connectionist calculations. We have used these results as part of the design of a programmable single chip microprocessor, SPERT. The reduced precision arithmetic permits the use of multiple arithmetic units per processor. Also, reduced precision operands make more efficient use of valuable processor-memory bandwidth. For our moderate-precision fixed-point arithmetic applications, SPERT represents more than an order of magnitude reduction in cost over systems with equivalent performance that use commercial DSP chips.     

Prediction of Core Losses of Three-Phase Distribution Transformer

Transformers are normally designed and built for use at rated frequency and sinusoidal load current. A non-linear load on a transformer leads to harmonic power losses which cause increased operational costs and additional heating in transformer parts. It leads to higher losses, early fatigue of insulation, premature failure and reduction of the useful life of the transformer. To prevent these problems, the rated capacity of transformer which supplies harmonic loads must be reduced. In this work, a typical 50 kVA three-phase distribution transformer with real practical parameters is taken under non-linear loads generated due to domestic loads. The core losses is evaluated using the three dimensional model of the transformer developed in FEM （finite element method） program based on valid model of transformer under high harmonic conditions. And finally a relation associated with core losses and amplitude of high harmonic order are reviewed ＆ analyzed and then a comparison is being carried out on the results obtained by different excitation current in transformer windings.     

Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics

Silicon photonics is a promising technology for addressing memory bandwidth limitations in future many-core processors. This article first introduces a new monolithic silicon-photonic technology, which uses a standard bulk CMOS process to reduce costs and improve energy efficiency, and then explores the logical and physical implications of leveraging this technology in processor-to-memory networks.     

Spherical reflector-absorber system with uniform concentration and normal incoming ray to absorber

A spherical reflector-absorber system with uniform concentration and normal incoming ray to the absorber is considered, in approximation of the sun as a point source. The corresponding system of integral-differential equations is solved by the series method and also by the Runge-Kutta method. Unique shapes of reflector and absorber are obtained.     

Perturbation of solutions of ordinary linear homogeneous differential equations of the second order

In this paper we give a method for peturbation of solutions of linear homogeneous differential equation of the second order.     

Use of a predictive colour model for managing the colour appearance of two‐colour woven fabrics

The aim of this study was to implement a two‐dimensional colour appearance model for prediction of the colour values of weft threads when the optical mixing of a two‐colour woven structure had to match the colour appearance of a single‐colour reference woven fabric. Five single‐colour woven fabrics were woven from five threads of similar hue. One of the samples was chosen as a reference, for which the colour appearance was the goal to be achieved in the two‐colour woven fabrics prepared with the other available warp threads and newly dyed weft threads. The colour values of dyed weft threads were predicted by a two‐dimensional colour appearance model. With dyed weft threads, managing the colour appearance of the two‐colour woven fabric was enabled to achieve the colour values of the reference. In the results, colour deviations between the predicted and measured colour values of weft threads revealed some limitations to the colour appearance model and performance of the dyeing process. After the production of the two‐colour woven fabric, the colour appearance matched the appearance of the reference, resulting in deviations of ΔE_CMC(2:1) = 1.2‐7.8. Moreover, the differences between theoretically predicted and measured colour values of the two‐colour woven fabric were evaluated as small, ranging from ΔE_CMC(2:1) = 1.5‐1.9. The results demonstrated the efficiency of implementing the colour appearance model and the dyeing process of weft threads as an approach to achieve the defined colour appearance of two‐colour woven fabrics, which with small colour deviations matches the colour of a single‐colour reference.