Development of a simple microsystems membrane probe card

Presented here are details of the development of a novel membrane integrated circuit (IC) probe card structure based on microsystems technology. The device design allows probing of both solder bumps and pads. A self-limiting sensor was integrated to prolong device lifetime. Comparison with and discussion of the use of modelling is made. Possible enhancements to the probing structure are discussed to improve alignment and measurements. Also shown is data using our microsystems probe card to access a simple IC device. Our device has a contact resistance of less than 0.5 Ω for a force of 0.004 N. A method to implement our probing structure for commercial application and the potential developments which can be made to improve its ease of use are then discussed.     

Polystyrene‐supported polyoxyethylene bound potassium permanganate as a heterogeneous oxidizing agent

Oxidation behavior of a 2 mol % divinylbenzene (DVB)‐crosslinked polystyrene‐supported permanganate function was investigated toward low molecular weight primary and secondary alcohols and aldehydes. The permanganate function was attached to a polystyrene support through cyclic polyoxyethylene (POE) units immobilized on the support. Contrary to the oxidations catalyzed by low molecular weight permanganate reagents, the oxidation of primary alcohol terminated in the aldehyde stage. The secondary alcohols were converted to the respective ketone and aldehyde to acid. The effect of the variable parameters similar to solvent, temperature, and reagent to substrate ratio was followed. Nonpolar cyclohexane was found to be the best solvent for the present study. Also the reactivity increased with increasing temperature. The oxidizing reagent possesses a long shelf life and could be recycled several times without reduction of capacity and mechanical stability. © 2003 Wiley Periodicals, Inc. J Appl Polym Sci 90: 3708–3717, 2003     

Prognostic significance of cathepsin-D in patients with breast cancer

The expression of the protease cathepsin-D has been evaluated using an immunohistochemical technique with a polyclonal antibody in paraffin-embedded tissue from 359 patients treated between the years 1975-1981 for Stage I and II breast cancer. One hundred and twenty seven patients (35%) have strongly positive, granular staining, 138 (38%) are intermediately stained in the cytoplasm, and in 94 (26%) no staining is observed. There is a strong positive association between expression of cathepsin-D and the presence of tumour in axillary lymph nodes (P < 0.006). Expression of the protease is associated with significantly poorer survival of patients in univariate analysis (P = 0.025); however, this is not independent of other tumour variables.     

Quantitation of Cefaclor in Pharmaceutical Dosage Forms Using High Performance Liquid Chromatography

A stability-indicating high-performance liquid chromatography for the quantitation of cefaclor in pharmaceutical dosage forms has been developed. The method is accurate and precise with a percent relative standard deviation of 1.2 based on 5 readings. A number of inactive ingredients present in the capsules and suspensions did not interfere with the assay procedure. The extraction procedure from the dosage forms is very simple. The recovery from the synthetic mixtures was quantitative. The capsules which had expired 3 years ago lost only 3% of the potency. The drug appears to be very sensitive to strong acids or bases since a 5 minute boiling caused 100% degradation of drug in both the solutions.     

A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme

This paper describes a 32-KB two-read, one-write ported L0 cache for 4.5-GHz operation in 1.2-V 130-nm dual-V/sub TH/ CMOS technology. The local bitline uses a leakage-tolerant self reverse-bias (SRB) scheme with nMOS source-follower pullup access transistors, while preserving robust full-swing operation. Gate-source underdrive of -220 mV on the bitline read-select transistors is established without external bias voltages or gate-oxide overstress. Device-level measurements in the 130-nm technology show 72/spl times/ bitline active leakage reduction, enabling low-V/sub TH/ usage, 40% bitline keeper downsizing, and 16 bitcells/bitline. 11% faster read delay and 2/spl times/ higher dc noise robustness are achieved compared with high-performance dual-V/sub TH/ bitline scheme. Sustained performance and robustness benefits of the SRB technique against conventional dynamic bitline with scaling to 100- and 70-nm technology is also presented.