High performance of silicided silicon-sidewall source and drain (S4D) structure

A silicided silicon-sidewall source and drain (S⁴D) structure is proposed for sub-0.1-μm devices. The merit of the S⁴D structure is that the series resistance of the source and drain is significantly reduced since the silicide layer is attached very close to the gate electrode and the silicon sidewall can be doped very highly. Thus, very high drain current drive can be expected, Another advantage of this structure is that the source and drain extensions are produced by the solid-phase diffusion of boron from the highly doped silicon-sidewall. Thus, shallow extensions with very high doping can be realized. A 75-nm gate length pMOSFET fabricated with this structure is shown to exhibit excellent electrical characteristics     

Calculation of Direct Tunneling Current through Ultra-Thin Gate Oxides Using Complex Band Models For SiO2

We report the calculation of gate leakage currents through the ultra-thin gate oxides (2.6–3.4 nm) in MOSFETs. We simulate J-V characteristics for the direct tunneling of valence electrons and inversion layer holes, which are measured using a charge separation technique. A two-band model is employed to express the complex band structure of the gate oxide, and its validity is discussed by calculating the complex band structure of -cristobalite based on the second nearest neighbor sp ³ s* tight-binding scheme.     

Power Optimization for SRAM and Its Scaling

With technology scaling, there is a strong demand for smaller cell size, higher speed, and lower power in SRAMs. In addition, there are severe constraints for reliable read-and-write operations in the presence of increasing random variations that significantly degrade the noise margin. To understand these tradeoffs clearly and find a power-delay optimal solution for scaled SRAM, sequential quadratic programming is applied for optimizing 6-T SRAM for the first time. The use of analytical device models for transistor currents and formulate all the cell-operation requirements as constraints in an optimization problem. Our results suggest that, for optimal SRAM cell design, neither the supply voltage (V_dd) nor the gate length (L_g) scales, due to the need for an adequate noise margin amid leakage and threshold variability and relatively low dynamic activity of SRAM. This is true even with technology scaling. The cell area continues to scale despite the nonscaling gate length (L_g) with only a 7% area overhead at the 22-nm technology node as compared to simple scaling, at which point a 3-D structure is needed to continue the area-scaling trend. The suppression of gate leakage helps to reduce the power in ultralow-power SRAM, where subthreshold leakage is minimized at the cost of increase in cell area     

Wannier-Stark oscillations in Zener tunneling currents

We have performed measurements of current-voltage characteristics at low temperatures in p-i-n diodes with a thin intrinsic region containing several (GaAs₅/(AlAs)₂ quantum wells. Under reverse bias, we found an oscillatory structure in the second derivative of the Zener tunneling current. The measurements agree well with theoretical calculations that are based on a transfer matrix approach and a realistic multi-band and multi-channel tight-binding scattering theory. The experiments show that Wannier-Stark oscillations in semiconductors occur in the d.c. current, in the regime of interband tunneling.     

An 0.18-μm CMOS for mixed digital and analog applications withzero-volt-Vth epitaxial-channel MOSFETs

An 0.18-μm CMOS technology with multi-V_ths for mixed high-speed digital and RF-analog applications has been developed. The V _ths of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFET's with zero-volt-V_th for RF analog circuits. The zero-volt-V_th MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD) at 750°C, the film quality is as good as the bulk silicon because high pre-heating temperature (940°C for 30 s) is used in H₂ atmosphere before the epitaxial growth. The epitaxial channel MOSFET shows higher peak g_m and f_T values than those of bulk cases. Furthermore, the g_m and f_T values of the epitaxial channel MOSFET show significantly improved performances under the lower supply voltage compared with those of bulk. This is very important for RF analog application for low supply voltage. The undoped-epitaxial-channel MOSFETs with zero-V_th will become a key to realize high-performance and low-power CMOS devices for mixed digital and RF-analog applications     

Electro-Thermally Coupled Power Optimization for Future Transistors and Its Applications

We report a novel electro-thermally coupled power-optimization methodology for future transistors. The methodology self-consistently yields the globally optimized total power and the corresponding temperature as a function of delay for a given set of transistors (bulk, double-gate FET, fully depleted SOI, and partially depleted SOI) at future technology nodes. When SPICE models are not necessarily available and simple device models are highly inadequate because of complex 2D device effects, these derived power/temperature versus delay curves serve as a comprehensive standard to compare any two transistors for future technology-node device selections. Because the power optimization is global (over various transistor parameters and includes leakage as well as dynamic power) and is self-consistently coupled to electro-thermal models, the methodology provides the optimum operational supply voltage (V_dd) and the device parameters (body thickness, equivalent oxide thickness, and gate metal work function) for future transistors targeting 45-nm technology node. Furthermore, it can be used to provide insight into advance nodes, device-specific hot-spot problems, multiple V_t, V_dd design for different functional blocks, transistor design, and evaluating the efficacy of novel thermal solutions such as superior thermal conductivity and subambient cooling.     

Supply and threshold-Voltage trends for scaled logic and SRAM MOSFETs

The authors show new guidelines for V/sub dd/ and threshold voltage (V/sub th/) scaling for both the logic blocks and the high-density SRAM cells from low power-dissipation viewpoint. For the logic operation, they have estimated the power and the speed for inverter gates with a fanout=3. They find that the optimum V/sub dd/ is very sensitive to switching activity in addition to the operation frequency. They propose to integrate two sets of transistors having different V/sub dd/s on a chip. In portions of the chip with high frequency or high switching activity, the use of H transistors in which V/sub dd/ and V/sub th/ are moderately scaled is helpful. On the other hand, in low switching activity blocks or relatively low frequency portions, the use of L transistors in which V/sub dd/ should be kept around 1-1.2 V is advantageous. A combination of H and L is beneficial to suppress power consumption in the future. They have investigated the yield of SRAM arrays to study the optimum V/sub dd/ for SRAM operation. In high-density SRAM, low V/sub th/ causes yield loss and an area penalty because of low static noise margin and high bit leakage especially at high temperature operation. V/sub th/ should be kept around 0.3-0.4 V from an area size viewpoint. The minimum V/sub dd/ for SRAM operation is found to be 0.7 V in this study. It is also found that the supply voltage for SRAM cannot be scaled continuously.