Design techniques for fault-tolerant systolic arrays

A systematic approach of designing fault-tolerant systolic architectures is proposed in this paper. In this approach, redundant computations are introduced at the algorithmic level by deriving three versions of a given algorithm. Fault-tolerant systolic array is constructed by merging the corresponding systolic array of the three versions of the algorithm. The merging method attempts to obtain the fault-tolerant systolic array at minimal cost in terms of area and speed. It is based on rescheduling input data, rearranging data flow, and increasing the utilization of the array cells. The resulting design can detect and tolerate all single permanent and temporary faults and the majority of the multiple fault patterns with high probability.     

Modeling,simulation, and prediction of global energy indices: a differential approach

Modeling, simulation, and prediction of global energy indices remain veritable tools for econometric, engineering, analysis, and prediction of energy indices. Thus, this paper differentially modeled, simulated, and non-differentially predicated the global energy indices. The state-of-the-art of the research includes normalization of energy indices, generation of differential rate terms, and regression of rate terms against energy indices to generate coefficients and unexplained terms. On imposition of initial conditions, the solution to the system of linear differential equations was realized in a Matlab environment. There was a strong agreement between the simulated and the field data. The exact solutions are ideal for interpolative prediction of historic data. Furthermore, the simulated data were upgraded for extrapolative prediction of energy indices by introducing an innovative model, which is the synergy of deflated and inflated prediction factors. The innovative model yielded a trendy prediction data for energy consumption, gross domestic product, carbon dioxide emission and human development index. However, the oil price was untrendy, which could be attributed to odd circumstances. Moreover, the sensitivity of the differential rate terms was instrumental in discovering the overwhelming effect of independent indices on the dependent index. Clearly, this paper has accomplished interpolative and extrapolative prediction of energy indices and equally recommends for further investigation of the untrendy nature of oil price.     

Recruiting the Host's Immune System to Target Helicobacter pylori's Surface Glycans

Due to the increased prevalence of bacterial strains that are resistant to existing antibiotics, there is an urgent need for new antibacterial strategies. Bacterial glycans are an attractive target for new treatments, as they are frequently linked to pathogenesis and contain distinctive structures that are absent in humans. We set out to develop a novel targeting strategy based on surface glycans present on the gastric pathogen Helicobacter pylori (Hp). In this study, metabolic labeling of bacterial glycans with an azide‐containing sugar allowed selective delivery of immune stimulants to azide‐covered Hp. We established that Hp's surface glycans are labeled by treatment with the metabolic substrate peracetylated N‐azidoacetylglucosamine (Ac₄GlcNAz). By contrast, mammalian cells treated with Ac₄GlcNAz exhibited no incorporation of the chemical label within extracellular glycans. We further demonstrated that the Staudinger ligation between azides and phosphines proceeds under acidic conditions with only a small loss of efficiency. We then targeted azide‐covered Hp with phosphines conjugated to the immune stimulant 2,4‐dinitrophenyl (DNP), a compound capable of directing a host immune response against these cells. Finally, we report that immune effector cells catalyze selective damage in vitro to DNP‐covered Hp in the presence of anti‐DNP antibodies. The technology reported herein represents a novel strategy to target Hp based on its glycans.     

Area efficient computing structures for concurrent error detection in systolic arrays

A method of designing testable systolic architectures is proposed in this paper. Testing systolic arrays involves mapping of an algorithm into a specific VLSI systolic architecture, and then modifying the design to achieve concurrent testing. In our approach, redundant computations are introduced at the algorithmic level by deriving two versions of a given algorithm. The transformed dependency matrix (TDM) of the first version is a valid transformation matrix while the second version is obtained by rotating the first TDM by 180 degrees about any of the indices that represent the spatial component of the TDM. Concurrent error detection (CED) systolic array is constructed by merging the corresponding systolic array of the two versions of the algorithm. The merging method attempts to obtain the self testing systolic array at minimal cost in terms of area and speed. It is based on rescheduling input data, rearranging data flow, and increasing the utilization of the array cells. The resulting design can detect all single permanent and temporary faults and the majority of the multiple fault patterns with high probability. The design method is applied to an algorithm for matrix multiplication in order to demonstrate the generality and novelty of our approach to design testable VLSI systolic architectures.This work has been supported by a grant from the Natural Sciences and Engineering Research Council of Canada.