Solving the Problem of Forbidden States in Discrete Event Systems: A Novel Systematic Method for Reducing the Number of Control Places

This paper deals with the problem of forbidden states in Discrete Event Systems modelled by non‐safe Petri Nets. To avoid these states, some Generalized Mutual Exclusion Constraints can be assigned to them. These constraints limit the weight sum of tokens in some places and can be enforced on the system using control places. When the number of these constraints is large, a large number of control places should be added to the system. In this paper, a method is presented to assign the small number of constraints to forbidden states using some states which cover the forbidden states. So, a small number of control places are added to the system leading to obtaining a maximally permissive controller.     

A new poly-Si TG-TFT with diminished pseudosubthreshold region: theoretical investigation and analysis

In this paper, we have proposed a new poly-Si triple-gate thin-film transistor (TG-TFT) where the front gate consists of two materials and three sections in order to reduce the OFF state leakage current without affecting the ON state voltage. We have used one and three grain-boundaries in the channel for analyzing the electrical characteristics of the poly-Si TG-TFT. The key idea in this paper is to make the dominant conduction mechanism in the channel to be controlled by the accumulation charge density modulation by the gate and not by the gate-induced grain barrier lowering. As a result, we demonstrate that the TG-TFT exhibits a highly diminished pseudosubthreshold region resulting in a substantial OFF state leakage current without any significant change in the ON voltage when compared to a conventional poly-Si TFT (C-TFT). Using two-dimensional and two-carrier device simulation, we have examined various design issues of the TG-TFT and provided the reasons for the improved performance.     

A Silicon on Nothing LDMOS with Two Air Pillars in Gate Insulator for Power Applications

Silicon - This paper proposes a new silicon on nothing lateral double-diffused metal-oxide-semiconductor with two air gaps in the gate insulator (SON-APG LDMOS). Utilizing air for the buried layer...     

Integration of Shuffled Frog Leaping Algorithm and Support Vector Regression for Prediction of Water Quality Parameters

Quality of surface water is a serious factor affecting human health and ecological systems. Accurate prediction of water quality parameters plays an important role in the management of rivers. Thus, different methods such as (support vector regression) SVR have been employed to predict water quality parameters. This paper applies SVR to predict eight water quality parameters including (sodium (Na⁺), potassium (K⁺), magnesium (Mg⁺²), sulfates (SO₄ ^?2), chloride (Cl^?), power of hydrogen (pH), electrical conductivity (EC), and total dissolved solids (TDS)) at the Astane station in Sefidrood River, Iran. To achieve an efficient SVR model, the SVR parameters should be selected carefully. Commonly, various techniques such as trial and error, grid search and metaheuristic algorithms have been applied to estimate these parameters. This study presents a novel tool for estimation of quality parameters by coupling SVR and shuffled frog leaping algorithm (SFLA) . Results of SFLA-SVR compared with genetic programming (GP) as a capable method in water quality prediction. Using SFLA-SVR, average of RMSE for training and testing of six combinations of data sets for all of the water quality parameters improved 57.4 % relative to GP. These results indicate that the new proposed SFLA-SVR tool is more efficient and powerful than GP for determining water quality parameters.     

High-blocking-voltage UMOSFETs with reformed electric field distribution

A high-performance vertical GaN metal–oxide–semiconductor field-effect transistor (MOSFET) with a U-shaped gate (UMOSFET) and high blocking voltage is proposed. The main concept behind this work is to reform the electric field distribution to achieve high blocking voltage. The proposed structure includes p-regions in the drift region, which we call reformed electric field (REF) regions. Simulations using the two-dimensional SILVACO simulator reveal the optimum doping concentration, and width and height of the REF regions to achieve the maximum depletion region at the breakdown voltage in the drift region. Also, the electric field distribution in the REF-UMOSFET is reformed by producing additional peaks, which decreases the common peaks under the gate trench. We discuss herein the impact of the height, width, and doping concentration of the REF regions on the ON-resistance (R_ON) and blocking voltage. The blocking voltage, specific ON-resistance, and figure of merit \( \left( {{\text{FOM}} = \frac{{V_{{{\text{BR}}}}^{2} }}{{R_{{{\text{ON}}}} }}} \right) \) are 1140 V, 0.587 mΩ cm² (V_GS = 15 V, V_DS = 1 V), and 2.214 GW/cm², respectively. The blocking voltage and FOM are increased by about 72 % and 171 % in comparison with a conventional UMOSFET (C-UMOSFET).     

Gain improvement and microwave operation of 4H–SiC MESFET with a new recessed metal ring structure

A new multi-recessed 4H-SiC MESFET with recessed metal ring for RF embedded circuits is proposed (MR2-MESFET). The key idea in the proposed structure is based on the elimination of the spaces adjacent to gate and stopped the depletion region extending towards drain and source and the reduction of the channel thickness between gate and drain to increase breakdown voltage (V_BR); meanwhile the elimination of the gate depletion layer extension to source/drain to decrease gate-source capacitance (C_gs). The influence of multi-recessed drift region and recessed metal ring structures on the characteristics of the MR2-MESFET is studied by numerical simulation. The optimized results show that the V_BR of the MR2-MESFET is 119% larger than that of the conventional 4H–SiC MESFET (C-MESFET); meanwhile maintain 85% higher saturation drain current. Therefore, the maximum output power density of the MR2-MESFET is 23.1 W/mm compared to 5.5 W/mm of the C-MESFET. Also, the cut-off frequency (f_T) and the maximum oscillation frequency (f_max) of 24.9 and 91.7 GHz are obtained for the MR2-MESFET compared to 11 and 40 GHz of the C-MESFET structure, respectively. The proposed MR2-MESFET shows a maximum stable gain (MSG) exceeding 23.6 dB at 3.1 GHz which is the highest gain yet reported for SiC MESFETs, showing the potential of this device for high power RF applications.     

Voltage difference engineering in SOI MOSFETs: A novel side gate device with improved electrical performance

We studied the impact of voltage difference engineering in a silicon-on-insulator metal oxide semiconductor field-effect transistor (SOI-MOSFET) and compared the performance to that of a conventional SOI-MOSFET (C-SOI). Our structure, called a SIG-SOI MOSFET, includes main and side gates with an optimum voltage difference between them. The voltage difference leads to an inverted channel as an electrical drain extension under the side gate. This channel creates a stepped potential distribution along the channel that it cannot be seen in the C-SOI MOSFETs. The voltage difference controls the channel properly and two-dimensional two-carrier device simulations revealed lower threshold voltage variations, larger breakdown voltage, higher voltage gain, lower hot carrier effects, improved drain-induced barrier lowering, lower drain conductance, higher unilateral power gain, and lower leakage current compared to a C-SOI device. Thus, our proposed structure has higher performance than a typical C-SOI structure.     

A silicon/indium arsenide source structure to suppress the parasitic bipolar-induced breakdown effect in SOI MOSFETs

We introduce Silicon/indium arsenide (Si/InAs) source submicron-device structure in order to minimize the impact of floating body effect on both the drain breakdown voltage and single transistor latch in ultra thin SOI MOSFETs. The potential barrier of valence band between source and body reduces by applying the Indium Arsenide (InAs) layer at the source region. Therefore, we can improve the drain breakdown by suppressing the parasitic NPN bipolar device and the hole accumulation in the body. As confirmed by 2D simulation results, the proposed structure provides the excellent performance compared with a conventional SOI MOSFET thus improving the reliability of this structure in VLSI applications.     

A novel high voltage lateral double diffused metal oxide semiconductor (LDMOS) device with a U-shaped buried oxide feature

A novel U-shape buried oxide lateral double diffused metal oxide semiconductor (LDMOS) is reported in this paper. The proposed structure features ionized charges in both sides of dielectric between source and gate region to enhance the breakdown voltage. The dielectric between drain and drift region affects on the breakdown voltage by adding a new peak in the electric field profile. Two dimensional simulation with a commercial software tool predicts significantly improved performance of the proposed device as compared to conventional LDMOS structures.