Architectural power analysis: The dual bit type method

This paper describes a novel strategy for generating accurate black-box models of datapath power consumption at the architecture level. This is achieved by recognizing that power consumption in digital circuits is affected by activity, as well as physical capacitance. Since existing strategies characterize modules for purely random inputs, they fail to account for the effect of signal statistics on switching activity. The dual bit type (DBT) model, however, accounts not only for the random activity of the least significant bits (LSB's), but also for the correlated activity of the most significant bits (MSB's), which contain two's-complement sign information. The resulting model is parameterizable in terms of complexity factors such as word length and can be applied to a wide variety of modules ranging from adders, shifters, and multipliers to register files and memories. Since the model operates at the register transfer level (RTL), it is orders of magnitude faster than gate- or circuit-level tools, but while other architecture-level techniques often err by 50-100% or more, the DBT method offers error rates on the order of 10-15%     

Optimizing throughput and resource utilization using pipelining: Transformation based approach

A simple formulation of pipelining: Pipelining withN stages is equivalent to retiming where the number of delays on all inputs or all outputs, but not both, is increased byN is used as the basis for a convenient and efficient treatment of pipelining in the design of application specific computers.Pipelining according to the objective function (throughput or resource utilization) and the latency is introduced. For two polynomial complexity pipelining classes, optimal algorithms are presented. For two other classes both proofs of NP-completeness and efficient probabilistic algorithms are presented. Both theoretical and experimental properties of pipelining are discussed and a relationship with other transformations is explored. Due to similar formulations for both software pipelining and the pipelining presented here, all results can be easily modified for use in compilers for general purpose computers. We have also developed a polynomial complexity algorithm for determining the iteration bound.This work was done while the first author was at the University of California, Berkeley.     

A 1-V heterogeneous reconfigurable DSP IC for wireless basebanddigital signal processing

A heterogeneous reconfigurable platform enables the flexible implementation of baseband wireless functions at energy levels between 10 and 100 MOPS/mW, six times higher than traditional digital signal processors. A 5.2 mm×6.7 mm prototype processor, targeted for voice compression, is implemented in a 0.25-μm 6-metal CMOS process, and consumes 1.8 mW at an average operation rate of 40 MHz. It combines an embedded microprocessor with an array of computational units of different granularities, connected by a hierarchical reconfigurable interconnect network     

Limitations and challenges of computer-aided design technology forCMOS VLSI

As manufacturing technology moves toward fundamental limits of silicon CMOS processing, the ability to reap the full potential of available transistors and interconnect is increasingly important. Design technology (DT) is concerned with the automated or semi-automated conception, synthesis, verification, and eventual testing of microelectronic systems. While manufacturing technology faces fundamental limits inherent in physical laws or material properties, design technology faces fundamental limitations inherent in the computational intractability of design optimizations and in the broad and unknown range of potential applications within various design processes. In this paper, we explore limitations to how design technology can enable the implementation of single-chip microelectronic systems that take full advantage of manufacturing technology with respect to such criteria as layout density performance, and power dissipation     

Ultralow-Power Design in Near-Threshold Region

Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.      

Standby supply voltage minimization for deep sub-micron SRAM

Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (V_DD) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when V_DD approaches DRV. The DRV model is verified using simulations as well as measurements from a 4 KB SRAM chip in a 0.13 μm technology. Due to a large on-chip variation, DRV of the 4 KB SRAM module ranges between 60 and 390 mV. Measurements taken at 100 mV above the worst-case DRV show that reducing the SRAM standby V_DD to a safe level of 490 mV saves 85% leakage power. Further savings can be achieved by applying DRV-aware SRAM optimization techniques, which are discussed at the end of this paper.     

Electrochemical sulfide oxidation from domestic wastewater using mixed metal-coated titanium electrodes

Hydrogen sulfide generation is a major issue in sewer management. A novel method based on electrochemical sulfide oxidation was recently shown to be highly effective for sulfide removal from synthetic and real sewage. Here, we compare the performance of five different mixed metal oxide (MMO) coated titanium electrode materials for the electrochemical removal of sulfide from domestic wastewater. All electrode materials performed similarly in terms of sulfide removal, removing 78 ± 5%, 77 ± 1%, 85 ± 4%, 84 ± 1%, and 83 ± 2% at a current density of 10 mA/cm² using Ta/Ir, Ru/Ir, Pt/Ir, SnO₂ and PbO₂, respectively. Elevated chloride concentrations, often observed in coastal areas, did not entail any significant difference in performance. Independent of the electrode material used, sulfide oxidation by in situ generated oxygen was the predominant reaction mechanism. Passivation of the electrode surface by deposition of elemental sulfur did not occur. However, scaling was observed in the cathode compartment. This study shows that all the MMO coated titanium electrode materials studied are suitable anodic materials for sulfide removal from wastewater. Ta/Ir and Pt/Ir coated titanium electrodes seem the most suitable electrodes since they possess the lowest overpotential for oxygen evolution, are stable at low chloride concentration and are already used in full scale applications.     

Redistribution of wastewater alkalinity with a microbial fuel cell to support nitrification of reject water

In wastewater treatment plants, the reject water from the sludge treatment processes typically contains high ammonium concentrations, which constitute a significant internal nitrogen load in the plant. Often, a separate nitrification reactor is used to treat the reject water before it is fed back into the plant. The nitrification reaction consumes alkalinity, which has to be replenished by dosing e.g. NaOH or Ca(OH)₂. In this study, we investigated the use of a two-compartment microbial fuel cell (MFC) to redistribute alkalinity from influent wastewater to support nitrification of reject water. In an MFC, alkalinity is consumed in the anode compartment and produced in the cathode compartment. We use this phenomenon and the fact that the influent wastewater flow is many times larger than the reject water flow to transfer alkalinity from the influent wastewater to the reject water. In a laboratory-scale system, ammonium oxidation of synthetic reject water passed through the cathode chamber of an MFC, increased from 73.8 ± 8.9 mgN/L under open-circuit conditions to 160.1 ± 4.8 mgN/L when a current of 1.96 ± 0.37 mA (15.1 mA/L total MFC liquid volume) was flowing through the MFC. These results demonstrated the positive effect of an MFC on ammonium oxidation of alkalinity-limited reject water.     

Low-power architectural synthesis and the impact of exploiting locality

Recently there has been increased interest in the development of high-level architectural synthesis tools targeting power optimization. In this paper, we first present an overview of the various architecture synthesis tasks and analyze their influence on power consumption. A survey of previously proposed techniques is given, and areas of opportunity are identified. We next propose a new architecture synthesis technique for low-power implementation of real-time applications. The technique uses algorithm partitioning to preserve locality in the assignment of operations to hardware units. Preserving locality results in more compact layouts, reduced usage of long high-capacitance buses, and reduced power consumption in multiplexors and buffers. Experimental results show reductions in bus and multiplexor power of up to 80% and 60%, respectively, resulting in 10–25% reduction in total power.