Positive temperature dependence of the electron impact ionizationcoefficient in In0.53Ga0.47As/InP HBTs

Impact ionization is a major limiting factor to the maximum operating voltage of InGaAs-based, high-speed transistors. In this work, data on the positive temperature dependence of the electron impact ionization coefficient α_n in In_0.53Ga_0.47As at medium-low electric fields are reported for the first time. The increase of α_n with temperature is opposite to the behavior normally observed in most semiconductors. This anomalous behavior implies the onset of a positive feedback between power dissipation and avalanche generation which may adversely affect the power handling capability of In_0.53Ga _0.47As-based devices, and which should be taken into account in device thermal modeling. In the experimental procedure, based on the measurement of the multiplication factor M-1 in npn In_0.53Ga _0.47As/InP Heterojunction Bipolar Transistors (HBT), particular care has been taken in order to rule out possible spurious, temperature-dependent contributions to the measured multiplication current     

Systematic characterization of Cl2 reactive ion etchingfor improved ohmics in AlGaN/GaN HEMTs

Pre-metal-deposition reactive ion etching (RIE) was performed on an Al_0.3Ga_0.7N/AlN/GaN heterostructure in order to improve the metal-to-semiconductor contact resistance. An optimum AlGaN thickness for minimizing contact resistance was determined. An initial decrease in contact resistance with etching time was explained in terms of removal of an oxide surface layer and/or by an increase in tunnelling current with the decrease of the AlGaN thickness. The presence of a dissimilar surface layer was confirmed by an initial nonuniform etch depth rate. An increase in contact resistance for deeper etches was experienced. The increase was related to depletion of the two-dimensional (2-D) electron gas (2-DEG) under the ohmics. Etch depths were measured by atomic force microscopy (AFM). The contact resistance decreased from about 0.45 Ωmm for unetched ohmics to a minimum of 0.27 Ωmm for 70 Å etched ohmics. The initial thickness of the AlGaN layer was 250 Å. The decrease in contact resistance, without excessive complications on device processing, supports RIE etching as a viable solution to improve ohmic contact resistance in AlGaN/GaN HEMTs     

Impact of unrealistic worst case modeling on the performance ofVLSI circuits in deep submicron CMOS technologies

The impact of process fluctuations on the variability of deep submicron (DSM) very large scale integration (VLSI) circuit performances is investigated in this paper. In particular, we show that as process dimensions stale down in the subhalfmicron region, the relative weight of process variability tends to increase, thus wearing down a non negligible portion of the benefits that are expected from minimum feature size scaling. We still show that in order to better exploit the advance of process technology, it is essential to adopt a realistic approach to worst case modeling [assigned probability technique (APT)]. The application of the APT technique to different test circuits designed in 0.35, 0.25, and 0.18 μm CMOS technologies with a power supply ranging from 3.3 V down to 1 V will demonstrate how the manufacturability of DSM designs is going to be a vital factor for the successful implementation of high-performance or low-power systems in 0.18 μm and lesser technologies     

2.1 A/mm current density AlGaN/GaN HEMT

The electrical performance of high current density AlGaN/GaN HEMTs is reported. 2 /spl times/ 75 /spl mu/m /spl times/ 0.7 /spl mu/m devices grown on sapphire substrates showed current densities up to 2.1 A/mm under 200 ns pulse condition. RF power measurements at 8 GHz and V/sub DS/=15 V exhibited a saturated output power of 3.66 W/mm with a 47.8% peak PAE.     

Pulsed measurements and circuit modeling of weak and strong avalanche effects in GaAs MESFETs and HEMTs

An extensive characterization of the on-state breakdown characteristics of GaAs based MESFETs and HEMTs has been carried out by means of DC and pulsed measurements and of circuit simulations. A computer-controlled, three-terminal Transmission Line Pulse (TLP) system with 50-100 ns pulse width and sub-ns risetime has been developed, which allows automated pulsed measurements of device I-V characteristics. The TLP system has been adopted for nondestructive measurements of the on-state breakdown characteristics of GaAs MESFETs and HEMTs up to unprecedented values of gate current density (I/sub G//W=30 mA/mm has been reached), in strong avalanche conditions. The device behavior in strong avalanche conditions is dominated by a parasitic bipolar effect (PBE) similarly to SOI and bulk Si MOSFETs. By taking into account this and other parasitic effects, an equivalent circuit model, suitable for SPICE simulations has been developed. The proposed model is capable of predicting the exact behavior of the gate and drain currents in both weak and strong avalanche conditions.     

Prediction of impact-ionization-induced snap-back in advanced Sin-p-n BJT's by means of a nonlocal analytical model for the avalanchemultiplication factor

The authors point out that when a triangular shape for the electric field in the base-collector space-charge region of an n-p-n Si BJT (bipolar junction transistor) is assumed, the electron mean energy can be calculated analytically from a simplified energy-balance equation. On this basis a nonlocal-impact-ionization model, suitable for computer-aided circuit simulation, has been obtained and used to calculate the output characteristics at constant emitter-base voltage (grounded base) of advanced devices. Provided the experimental bias-dependent value of the base parasitic resistance is accounted for in the device model, the base-collector voltage at which impact-ionization-induced snap-back occurs can be accurately predicted     

Impact ionization and light emission in InAlAs/InGaAsheterostructure field-effect transistors

We present measurements on impact ionization effects, real space transfer of holes and electrons, and light emission occurring in n-channel InAlAs/InGaGs heterostructure Field-Effect Transistors based on InP operated at high electric fields and at different temperatures. The channel electrons heated by the lateral electric field give rise to impact ionization and light emission. By comparing the electrical characteristics and the integrated light intensity in different energy ranges and at different temperatures, we were able to identify two main different light emission mechanisms: conduction to conduction-band transitions for low energy photons and conduction to valence-band transitions for high energy photons. The correlation between the gate current and the light intensity allowed us to separately evaluate the electron and hole components of the gate current     

An Investigation of the Electrical Degradation of GaN High-Electron-Mobility Transistors by Numerical Simulations of DC Characteristics and Scattering Parameters

The effects of direct-current (DC) stress on GaN high-electron-mobility transistors (HEMTs) are investigated by means of numerical simulations, by which the creation of an acceptor trap in the AlGaN barrier layer was correlated to the observed experimental degradation. An increase in the trap concentration induces a worsening of the saturated current I _DSS, transconductance g _m, and output conductance g _O. An increase in the length of the trapping region induces a degradation of I _DSS and g _m, but can reduce g _O. Analysis of scattering parameters in the saturation region shows that the cutoff frequency f _T matches the trend of g _m.     

Development of “kink” in the output I–V characteristics of pseudomorphic hemt's after hot-electron accelerated testing

Large decreases in the drain current in the linear and low V_ds region followed by a “kink” in the output I_d-V_ds characteristics have been found after hot electron stress test in AlGaAs/InGaAs/GaAs power pseudomorphic HEMT's. Decrease in the transconductance measured in linear region, increase in the drain parasitic resistance and trasconductance frequency dispersion have also been observed and attributed to the generation of electron traps in the gate-to-drain access region.     

Parasitic effects and long term stability of InP-based HEMTs

A study of InP based HEMTs implemented with different process options will be reported. It will be demonstrated that devices with an InP etch stopper layer or with a narrow lateral gate recess region do not present any kink effect, neither any transconductance frequency dispersion, g_m(f) and a stable behavior with respect to hot electron aging is observed. The opposite occurs in devices without the InP etch stopper layer and a wide lateral gate recess region. The data presented confirm the effectiveness of an InP passivating layer in improving the reliability of advanced InP-HEMTs, and point out at the free InAlAs surface as responsible for the observed instabilities (kink effects, g_m(f) dispersion).