排序方式: 共有6条查询结果,搜索用时 15 毫秒
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Silicon - This paper presents, analytical modeling of surface potential,threshold voltage and DIBL for a Dual-Metal Double-Gate Gate-All-Around (DM-DG-GAA) MOSFET considering the parabolic... 相似文献
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Visweswara Rao Samoju Pramod Kumar Tiwari 《International Journal of Numerical Modelling》2016,29(4):695-706
In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Qinv) at the ‘virtual‐cathode’ reaches to a critical charge Qth. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd. 相似文献
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Chitlu Subhasri Bhaskara Rao Jammu L. Guna Sekhar Sai Harsha Nalini Bodasingi Visweswara Rao Samoju 《International Journal of Circuit Theory and Applications》2021,49(1):128-141
Among all the arithmetic operations, division operation takes most of the clock cycles resulting in more path delay and higher power consumption. Many algorithms, including logarithmic division (LD), have been implemented to reduce the critical path delay and power consumption of division operation. However, there is a high possibility to further reduce these vital issues by using the novel approximate LD (ALD) algorithm. In the proposed ALD, a truncation adder is used for mantissa addition. Using this adder, the power delay product (PDP) and normalized mean error distance (NMED) are minimized. From the error analysis and hardware evaluation, it is observed that the proposed ALD using truncation adder (ALD‐TA) with an appropriate number of inexact bits achieve lower power consumption and higher accuracy than existing LDs with exact units. The normalized mean error distance of 8‐, 16‐, and 32‐bit ALD‐TA is compared with LDs of same bits and observed a decrease of up to 21%, 20%, and 21%, and the PDP has a reduction of up to 33%, 51%, and 72%, respectively. Application of ALD‐TA to image processing shows that high performance can be achieved by using ALDs than exact LDs. 相似文献
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Pramod Kumar Tiwari Visweswara Rao Samoju Thandva Sunkara Sarvesh Dubey Satyabrata Jit 《Journal of Computational Electronics》2016,15(2):516-524
In this paper, an analytical model of the threshold voltage for short-channel symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs) is presented. The three-dimensional (3D) Poisson equation in cylindrical coordinates has been solved with suitable boundary conditions to find the surface potential along the channel length. The inversion charge density \((Q_{inv} )\) has been calculated in the channel region of the device in the subthreshold regime of device operation, using the Boltzmann relationship. Subsequently, the calculated inversion charge density \((Q_{inv} )\) has been equated to a threshold charge density \((Q_{th})\) in order to find the threshold voltage \((V_{th})\) expression. The effect of physical device parameters, including the tube thickness, on the threshold voltage and drain induced barrier lowering (DIBL) of the device has been discussed. The model results have been verified with the simulation data obtained by the device simulation software ATLAS. 相似文献
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Ramesh L. Moparthi S. Tiwari P. K. Samoju V. R. Saramekala G. K. 《Semiconductors》2020,54(10):1290-1295
Semiconductors - In this paper, the electrical properties of a double-gate dual-active-layer (DG-DAL) thin-film transistor (TFT) are investigated. To increase the ON-current and pixel intensity,... 相似文献
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