A new method for manufacturing nanostructured electrodes on glass substrates

The present paper describes a new method for manufacturing a nanostructured porous layer of TiO₂ on a conducting glass substrate for use in a dye-sensitized photoelectrochemical cell. The method involves deposition of a layer of semiconductor particles onto a conducting substrate and compression of the particle layer to form a mechanically stable, electrically conducting, and porous nanostructured film at room temperature. Photoelectrochemical characteristics and morphology of the resulting nanostructured films are presented. The potential use of the new manufacturing method in the future applications of nanostructured systems is discussed.     

Consistent modeling of capacitances and transit times of GaAs-based HBTs

This paper investigates how time delays and capacitances observed under small-signal conditions can be consistently accounted for in heterojunction bipolar transistor (HBT) large-signal models. The approach starts at the circuit level by mapping the large-signal equivalent circuit (which consists of charge and current sources) to the well-known small-signal circuit (which consists of capacitances, transit-time, and resistances). It is shown that and how bias dependent charge sources at either pn-junction impact transit-time, base-collector capacitance, and their mutual dependence. It is demonstrated for the example of a GaAs-based HBT that the interrelation of the elements is observed in measurements as predicted. The results of the investigation enhance understanding of HBT model characteristics and provide a criterion to check model consistency.     

Crystallographic electron microscopy

We present a family of techniques for the transmission electron microscope that generate surface zone-axis patterns. These patterns display the variation of the diffracted-beam intensity as a function of the angle of the incident electrons. The conditions of the experiments are those of reflection high-energy electron diffraction at near grazing incidence. The techniques are: surface convergent-beam diffraction, a surface analogue of the Tanaka method and a modified double-rocking scheme. Experimental results are presented for diffraction from surfaces of MgO and MoS₂. We anticipate that surface zone-axis patterns (surface ZAPs) will become established as an important tool for surface characterization, especially when used in conjunction with high-resolution surface imaging and surface energy loss spectroscopy; surface ZAPs may be expected to play, in surface analysis, a role analogous to that played by convergent-beam diffraction in normal transmission electron microscopy.     

Putting it all together – Formal verification of the VAMP

In the verified architecture microprocessor (VAMP) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts, pipelined fully IEEE compatible dual precision floating point unit with variable latency, and separate instruction and data caches. The verification has been carried out in the theorem proving system PVS. The processor has been implemented on a Xilinx FPGA. A shorter version of this article with the title “Instantiating uninterpreted functional units and memory system: functional verification of the VAMP” appeared in [8]. The work reported here was done while all the authors were with Saarland University.     

Analysis of the Survivability of GaN Low-Noise Amplifiers

This paper presents a detailed analysis of the stressing mechanisms for highly rugged low-noise GaN monolithic-microwave integrated-circuit amplifiers operated at extremely high input powers. As an example, a low-noise amplifier (LNA) operating in the 3-7-GHz frequency band is used. A noise figure (NF) below 2.3 dB is measured from 3.5 to 7 GHz with NF<1.8 dB between 5-7 GHz. This device survived 33 dBm of available RF input power for 16 h without any change in low-noise performance. The stress mechanisms at high input powers are identified by systematic measurements of an LNA and a single high electron-mobility transistor in the frequency and time domains. It is shown that the gate dc current, which occurs due to self-biasing, is the most critical factor regarding survivability. A series resistance in the gate dc feed can reduce this gate current by feedback, and may be used to improve LNA ruggedness     

Fabrication and selective surface modification of 3-dimensionally textured biomedical polymers from etched silicon substrates

A new method is described for producing biomedically relevant polymers with precisely defined micron scale surface texture in the x, y, and z planes. Patterned Si templates were fabricated using photolithography to create a relief pattern in photoresist with lateral dimensions as small as 1 micron. Electroless Ni was selectively deposited in the trenches of the patterned substrate. The Ni served as a resilient mask for transferring the patterns onto the Si substrate to depths of up to 8.5 microns by anisotropic reactive ion etching with a fluorine-based plasma. The 3-dimensional (3-D) textured silicon substrates were used as robust, reusable molds for pattern transfer onto poly (dimethyl siloxane), low density poly (ethylene), poly (L-lactide), and poly (glycolide) by either casting or injection molding. The fidelity of the pattern transfer from the silicon substrates to the polymers was 90 to 95% in all three planes for all polymers for more than 60 transfers from a single wafer, as determined by scanning electron microscopy and atomic force microscopy. Further, the 3-D textured polymers were selectively modified to coat proteins either in the trenches or on the mesas by capillary modification or selective coating techniques. These selectively patterned 3-D polymer substrates may be useful for a variety of biomaterial applications.