A Fast Vision-inertial Odometer Based on Line Midpoint Descriptor

Machine Intelligence Research - Visual simultaneous localization and mapping (VSLAM) are essential technologies to realize the autonomous movement of vehicles. Visual-inertial odometry (VIO) is...     

Effect of extrinsic impedance and parasitic capacitance on figure of merit of RF MOSFET

This paper investigates the impact of source/drain impedance, gate-to-bulk capacitance, and gate resistance on device properties from 0 to 50 GHz for 0.13-/spl mu/m MOSFETs. Better device characteristics (g/sub m/ and C/sub gg/) can be found on MOSFETs with lower metal (or source/drain) resistance. But the best frequency characteristics (f/sub T/ and f/sub max/) occurred on MOSFETs with medium metal (or source/drain) resistance due to the increased interconnection capacitances. For radio frequency MOSFETs with finger-gate structure, better high-frequency behavior occurred on devices with medium finger-gate width W/sub f/ because of the tradeoff between gate (or source/drain) resistance and parasitic capacitance.     

Reliability of the doping concentration in an ultra-thin body and buried oxide silicon on insulator (SOI) and comparison with a partially depleted SOI

This study compares the reliability of nMOSFETs with low- and high-doped ultra-thin body and buried oxide (UTBB) with fully depleted (FD) and partially depleted (PD) silicon on insulator (SOI). The high-doped devices display lower off-current leakage performance but more degradation in both hot-carrier stress (HCS) and positive bias temperature instability (PBTI) test at both room temperature and elevated temperature compared with the low-doped devices. The PBTI test indicates that the high-doped devices induce high tunneling leakage and that the degradation is highly associated with temperature. The degradation stabilizes with an increase in stress time. The thinner PD-SOI demonstrates low variation at the threshold voltage and low drive current under HCS. The FD-SOI has better drain leakage control than the PD-SOI.     

Design and fabrication of deep submicron CMOS technology compatible suspended high-Q spiral inductors

In this paper, deep submicron complementary metal-oxide-semiconductor (CMOS) process compatible high-Q suspended spiral on-chip inductors were designed and fabricated. In the design, the electromagnetic solver, SONNET, and the finite element program, ANSYS, were used for electrical characteristics, maximum endurable impact force, and thermal conduction simulations, respectively. Based on the design, suspended spiral inductors with different air cavity structures, i.e., diamond opening, circle opening, triangle opening, and full suspended with pillar supports were developed for various applications. Among these structures, the suspended inductor with pillar support possesses the highest Q/sub max/ (maximum of quality factor) of 6.6 at 2 GHz, the least effective dielectric constant of 1.06, and the lowest endurable impact force 0.184 Newton. On the other hand, the spiral inductor with diamond opening has a lowest Q/sub max/ of 4.3, the largest effective dielectric constant of 3.44 and highest endurable impact force 4 Newton. The former is suitable for station telecommunication applications in which the mechanical vibration is not a serious concern, while the latter can be used for mobile telecommunication applications subject to strong mechanical vibrations. Additionally, the conventional on-chip spiral inductor embraced by SiO/sub 2/ with a dielectric constant of 4 was prepared for comparison and found its Q/sub max/ is 3.8 at 1.2 GHz.     

Substrate noise-coupling characterization and efficient suppression in CMOS technology

This brief investigates the substrate noise coupling using S-parameters measurement. Radio frequency domain analysis shows that the noise isolation is strongly dependent on layout geometry, including the parameters such as p-n junction, physical separation distance, guard ring (GR), and deep n-well (DNW). We found that the noise coupling can be efficiently diminished by incorporating GR and DNW structures.     

The impacts of high tensile stress CESL and geometry design on device performance and reliability for 90 nm SOI nMOSFETs

The thickness effects of high-tensile-stress contact etch stop layer (HS CESL) and impact of layout geometry (length of diffusion and gate width) on mobility enhancement of 100/(100) 90 nm SOI nMOSFETs were studied in detail. Additionally, we also inspected the low frequency characteristic with low-frequency noise investigation for FB-SOI nMOSFETs. Experimental results show that devices with 1100 Å HS CESL possess worse characteristics and hot-carrier-induced degradations than devices with 700 Å HS CESL due to serious stress-induced defects happen. The lower plateau of Lorentzian noise spectrum observed from input-referred voltage noise (S_vg) implies higher leakage current for the devices with 1100 Å HS CESL. On the other hand, we found that devices with narrow gate widths possess higher driving capacity because of larger fringing electric fields and higher compressive stress in direction perpendicular to the channel. Owing to the more serious impact of compressive stress in direction parallel to the channel, the device performance was degraded particularly for devices with shorter LOD.     

Temperature dependency of 0.1 μm partially depleted SOI CMOSFET

This work investigates the floating body effect (FBE) on the partially depleted SOI devices at various temperatures for high-performance 0.1 μm MOSFET. The thermal effect on the device's characteristics was investigated with respect to the body contacted MOSFET (BC-SOI) and floating body MOSFET without body contacted (FB-SOI). It is found that the threshold voltage (Vth) and the off state drain current (I_OFF) of the BC-SOI devices are more temperature sensitive than those of the FB-SOI devices. For operation at higher temperatures, there is no apparent difference in driving capability between the BC-SOI and FB-SOI MOSFETs     

A high current gain gate-controlled lateral bipolar junction transistor with 90 nm CMOS technology for future RF SoC applications

A CMOS-compatible gate-controlled lateral BJT (GC-LBJT) was prepared with a conventional 90 nm CMOS technology for radio frequency system-on-chip (RF SoC) applications. The emitter injection efficiency and the doping profile in P-well were optimized by properly controlling source, drain, and well implants. Consequently, the GC-LBJT with a gate length of 0.15 μm can achieve a current gain over 2000 and 17/19 GHz for the f_T/f_max, respectively, which are 1000%, 200%, and 60% improvements in current gain, f_T and f_max, respectively as compared to the LBJT reported previously.     

Frequency divider design using the combination of transistors and passive devices

The behavior of a frequency divider circuit using negative differential resistance (NDR) circuit, which is composed of resistor (R) and bipolar junction transistor (BJT), is studied. This frequency divider is mainly made of an R-BJT-NDR circuit, an inductor, and a capacitor. The operation is based on the long-period behavior of the NDR-based chaos circuit. We investigate the effects of the input signal frequency, bias, and amplitude on its operation. The results show that the dividing ratio can be selected by modulating these parameters. Finally, we demonstrate the high-frequency consideration and characteristic of this frequency divider.     

Hot-carrier-induced degradation for partially depleted SOI 0.25-0.1 /spl mu/m CMOSFET with 2-nm thin gate oxide

Hot-carrier-induced degradation of partially depleted SOI CMOSFETs was investigated with respect to body-contact (BC-SOI) and floating-body (FB-SOI) for channel lengths ranging from 0.25 down to 0.1 /spl mu/m with 2 nm gate oxide. It is found that the valence-band electron tunneling is the main factor of device degradation for the SOI CMOSFET. In the FB-SOI nMOSFET, both the floating body effect (FBE) and the parasitic bipolar transistor effect (PBT) affect the hot-carrier-induced degradation of device characteristics. Without apparent FBE on pMOSFET, the worst hot-carrier stress condition of the 0.1 /spl mu/m FB-SOI pMOSFET is similar to that of the 0.1 /spl mu/m BC-SOI pMOSFET.