Functional characteristics of Bi2Sr2Ca2Cu3O10 + δ/ZrN composites

We present the results of investigation of the magnetic, transport, structural, and mechanical properties of composites obtained by introducing finely dispersed zirconium nitride into a matrix of a Bi₂Sr₂Ca₂Cu₃O_{10 + δ} (Bi2223) high-temperature superconductor. It is established that the introduction of ZrN particles in the range of very small concentrations (0.1–0.3 wt %) leads to a significant (more than threefold) increase in the critical current density of Bi2223 and increases the density of the composite, while the microhardness of the superconducting phase remains unchanged.     

区块链上基于B+树索引结构的密文排序搜索方案

为了克服云存储不可信及云存储中密文检索效率低的问题,该文提出区块链上基于B+树的密文排序可搜索加密方案。该方案结合区块链技术解决了在互不了解的多方建立可靠信任的问题;使用向量空间模型降低了文本的复杂性实现了高效的文本检索系统;采用B+树的索引结构提高了区块链上密文交易的检索速度;利用加权统计(TF-IDF)算法实现了多关键词查询结果的排序。在随机预言机模型下,证明该方案是适应性不可区分安全的,通过效率对比分析,表明该方案在区块链上实现了高效的密文检索。     

Computationally efficient direction-of-arrival estimation of non-circular signal based on subspace rotation technique

In order to solve the problem that the high computational burden of the multiple signal classification algorithm of non-circular signal (NC-MUSIC) in direction-of-arrival (DOA) estimation,a novel computationally efficient DOA estimation algorithm based on subspace rotation technique was proposed.Firstly,the partitioning of noise subspace matrix and the subspace rotation technique (SRT) were used to construct a new reduced-dimension noise subspace.Then,the two-dimensional peak searching was converted to the one-dimensional peak searching on the basis of the separation of variables and the orthogonality between the new reduced-dimension noise subspace and the space spanned by the columns of the extended manifold matrix.The proposed algorithm can enhance the computational efficiency by means of the conversion of the two-dimensional peak searching into the one-dimensional peak searching and the removal of redundant computations.Theoretical analysis and simulation results show that the proposed algorithm can reduce the computational complexity to less than 5% as compared to NC-MUSIC algorithm on the premise of ensuring the accuracy of DOA estimation.Especially,the efficiency advantage of the proposed algorithm is more obvious in scenarios where the large numbers of sensors are required.     

A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging

Temporal unreliability due to aging, such as Negative-Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) effects etc., in the CMOS circuits may not appear just after the chip production, instead it becomes apparent when it is used under certain workload and environmental conditions over time. Identifying aged paths that may become critical to circuit performance, is a real challenge for many researchers and reliability engineers. In this work, firstly we identify a set of parameters that impact the circuit performance under aging and use them in the proposed algorithm which is substantially faster than commercially available SPICE simulator with an approx 94% accuracy in estimating path delays. Secondly, we explore the possibility of using the proposed methodology, instead of using time expensive SPICE and pessimistic static timing analysis (STA), to identify a set of speed-limiting paths under aging. Experimental results demonstrate the effectiveness of the proposed algorithm and the associated methodology in comparison to SPICE simulated results.     

Low-Area Wrapper Cell Design for Hierarchical SoC Testing

System-on-chip (SoC) integrated circuits are designed and fabricated with multiple levels of hierarchy. However, most previous works on wrapper design, test access mechanism optimization and test scheduling did not take care of the hierarchy properly, thus the corresponding test schedules were often invalid for SoCs with hierarchical cores. We propose a low-area wrapper cell design which can treat SoCs with hierarchy properly and allows simultaneous testing of parent and child cores. The proposed cell uses 13%∼23% less area than a recently proposed cell design in equivalent gate count. As a result we achieve up to 21% area reduction for hierarchical ITC ’02 SoCs compared to the most recently proposed designs.     

Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester

Numerous solutions have been proposed to reduce test data volume and test application time during manufacturing testing of digital devices. However, time to market challenge also requires a very efficient debug phase. Error identification in the test responses can become impractically slow in the debug phase due to large debug data, slow tester speed, and limited memory of the tester. In this paper, we investigate the problems and solutions related to using a relatively slow and limited memory tester to observe the at-speed behavior of fast circuits. Our method can identify all errors in at-speed scan BIST environment without any aliasing and using only little extra overhead by way of a multiplexer and masking circuit for diagnosis. Our solution takes into account the relatively slower speed of the tester and the reload time of the expected data to the tester memory due to limited tester memory while reducing the test/debug cost. Experimental results show that the test application time by our method can be reduced by a factor of 10 with very little hardware overhead to achieve such advantage.     

Simulating program disturb faults in flash memories using SPICE compatible electrical model

Electrical simulation is an important tool that enables designers to evaluate different design alternatives and assess their performance. In memory technology, these tools are used to study the performance of different cell structures and implementations. In this paper we use such simulations to study the impact of defects on the performance of flash memory bitcells. In particular, using a device level simulator, we develop a SPICE compatible model to simulate the operation of a 1T flash bitcell. We then describe a fault injection technique that can be used, in conjunction with the model, to simulate faulty cell behavior. The model is used to simulate different defects in the oxide layer of the flash core memory element. The impact of defects on bitcell behavior under disturb and normal operations is investigated and evaluated. The model is demonstrated to be valuable to evaluate the appropriateness of the logic tests and stress tests used to detect such defects in flash memories.     

Verification of wind resource study of a Scottish region

In a survey of the practical wind energy resource present in the Tayside Region of Scotland it was estimated that over 1500 km² of land is suitable for wind energy development in the Region after consideration of a range of physical, technical and institutional factors. Wind speed data for this survey was obtained from the Energy Technology Support Unit (ETSU) UK Wind Speed Data Package. To verify the wind speeds obtained from the ETSU package a representative sample of sites in and around the identified areas of potential in Tayside were modelled for mean annual wind speed using the Wind Atlas Analysis and Application Program (WA^sP). The wind speeds for the sites obtained from the WA^sP analysis were compared with those obtained from the ETSU UK Wind Speed Data Package and conclusions drawn as to the reliability of the Tayside wind energy survey and the general applicability of the ETSU package for broad wind energy resource assessment.