Equal‐channel angular rolling (ECAR) is a continuous severe plastic deformation process. In this process, severe shear strains apply to the sheet. This strain increases the yield or ultimate strength of sheet without significant change in sheet dimension. In this paper, the effect of ECAR process on mechanical properties and fatigue life of manufactured sheets will be studied. Four AA5083 samples have been prepared and annealed for obtaining stress‐free samples. Three samples have been rolled by the ECAR process with one, two and three passes of rolling, respectively. Mechanical tests including tensile test, hardness and axial fatigue tests have been carried out on prepared samples. Fatigue tests have been implemented according to a strain‐based approach with a constant strain ratio equal to 0.75 and 0.5 Hz frequency of loading. All of the tests have been carried out in controlled laboratory conditions. Results show that the ultimate tensile strength of samples increases with increasing the pass of rolling. Also, the maximum elongation of samples decreases. Maximum elongation was 17% in annealed samples, while it decreases to 10% in samples with three passes of rolling. The hardness of samples has been measured, and the results show an increase in hardness for a higher pass of the ECAR process. Fatigue test results show that fatigue life of AA5083 samples decreases in manufactured sheets of the ECAR process. Also, cyclic softening has been observed in the ECARed sample. The fracture surfaces of samples after fatigue test have been observed with a scanning electron microscope. A comparison of fracture surfaces confirms that the crack growth was intergranular in annealed samples while it changes in ECARed samples to transgranular. 相似文献
Process capability indices such as Cp are used extensively in manufacturing industries to assess processes in order to decide about purchasing. In practice, the parameter for calculating Cp is rarely known and is frequently replaced with estimates from an in-control reference sample. This article explores the optimal sample size required to achieve a desired error of estimation using absolute percentage error of different Cp estimates. Moreover, some practical tools are created to allow practitioners to find sample size in different situations. 相似文献
Soil contamination by petroleum contaminants and their derivatives has harmful effects on the environment, including groundwater and marine contamination and on the geotechnical properties of the soil. It decreases the soil strength, bearing capacity of foundations, and slope and trench stability. Petroleum contaminants can also alter the structure of cohesive granular soil. The present study examined the effect of acidic sludge and dirt filter contaminants from a burnt oil refinery on the compaction parameters and strength of clayey sand. Proctor compaction and direct shear tests were performed on soil samples containing 0%, 3%, 6%, and 9% of these pollutants. Direct shear tests were performed at different depths and stresses on soil samples from sandy soil contaminated with the residue from a burnt oil refinery. The results showed that with approximately 4 to 5% increase in pollution, the maximum dry soil unit weight increases and decreases with the addition of more contaminants. Also, the friction and dilatancy angles of the soil decreased. The sample containing 9% pollutants recorded the most significant decrease in these values. The effect of surface-active agents on acidic sludge caused an increase in the Van der Waals force between the particles, resulting in an increase in soil cohesion. Contamination with 47.7% SiO2 from the dirt filter increased the soil cohesion parameter. Under similar experimental and loading conditions, an increase in the acidic sludge and dirt filter contents decreased the soil shear strength and dilatancy angle.
Synthesis of reversible logic has received significant attention in the recent years and many synthesis approaches for reversible circuits have been proposed so far. In this paper, a library-based synthesis methodology for reversible circuits is proposed where a reversible specification is considered as a permutation comprising a set of cycles. To this end, a pre-synthesis optimization step is introduced to construct a reversible specification from an irreversible function. In addition, a cycle-based representation model is presented to be used as an intermediate format in the proposed synthesis methodology. The selected intermediate format serves as a focal point for all potential representation models.In order to synthesize a given function, a library containing seven building blocks is used where each building block is a cycle of length less than 6. To synthesize large cycles, we also propose a decomposition algorithm which produces all possible minimal and inequivalent factorizations for a given cycle of length greater than 5. All decompositions contain the maximum number of disjoint cycles. The generated decompositions are used in conjunction with a novel cycle assignment algorithm which is proposed based on the graph matching problem to select the best possible cycle pairs. Then, each pair is synthesized by using the available components of the library. The decomposition algorithm together with the cycle assignment method are considered as a binding method which selects a building block from the library for each cycle. Finally, a post-synthesis optimization step is introduced to optimize the synthesis results in terms of different costs.To analyze the proposed methodology, various experiments are performed. Our analyses on the available reversible benchmark functions reveal that the proposed library-based synthesis methodology can produce low-cost circuits in some cases compared with the current approaches. The proposed methodology always converges and it typically synthesizes a give function fast. No garbage line is used for even permutations. 相似文献
In the past decade, successive approximation register (SAR) analog-to-digital converter (ADC) has become a popular topology in a wide range of resolutions and sampling rates. This paper investigates methods to improve the energy-and-area efficiency of the SAR ADCs by focusing on the design of the internal digital-to-analog converter (DAC). Different hybrid resistive–capacitive DACs are studied in detail. It is shown that more than an order of magnitude improvement in energy efficiency of the DAC is achievable. The conditions for such an improvement are discussed. 相似文献