高性能混凝土的超高泵送检测技术研究

随着泵送高度的增加,输送压力不断提高,容易造成混凝土离析、堵管等诸多问题,如何对泵送混凝土进行有效的检测便成为工程能否顺利完成的重中之重。本文通过研制开发一套高性能混凝土可泵性检测设备,并使用该套设备检测混凝土的相关泵送性黏性以及混凝土拌合物的流动性,间隙通过性和抗离析性来研究泵送混凝土的泵送性,最终根据实验结果提出该套设备的相关参数,辅助坍落度筒对泵送混凝土的可泵性进行有效准确的检测,给超高泵送工程提供指导。     

电荷共享对于CMOS逻辑门单粒子瞬态响应的影响

随着CMOS工艺继续缩小,单粒子瞬态脉冲已经成为航天用数字电路的重要故障来源。同时,相邻晶体管之间的电荷共享也随之增加并导致组合电路中单粒子瞬态脉宽缩短,即脉宽抑制效应。之前的文献提出了PMOS到PMOS的脉宽抑制,而本文提出了三种新的脉宽抑制机理(NMOS到PMOS,PMOS到NMOS和NMOS到NMOS),并且通过90纳米三维工艺混合仿真进行了验证。本文的贡献主要有以下三点：1）除了PMOS到PMOS的情况,90纳米工艺下脉宽抑制在PMOS到NMOS和NMOS到NMOS中同样比较明显;2）脉宽抑制效应总体上与粒子入射能量关系较弱,而与粒子入射角度和版图结构(晶体管间距和N阱接触)关系较强。3）紧凑的版图和级联反向单元可以用来促进组合电路中的单粒子瞬态脉宽抑制效应。     

A new FPGA architecture suitable for DSP applications

A new FPGA architecture suitable for digital signal processing applications is presented.DSP modules can be inserted into FPGA conveniently with the proposed architecture,which is much faster when used in the field of digital signal processing compared with traditional FPGAs.An advanced 2-level MUX(multiplexer) is also proposed.With the added SLEEP MODE PASS to traditional 2-level MUX,static leakage is reduced.Furthermore, buffers are inserted at early returns of long lines.With this kind of buffer,the delay of the long line is improved by 9.8%while the area increases by 4.37%.The layout of this architecture has been taped out in standard 0.13μm CMOS technology successfully.The die size is 6.3×4.5 mm~2 with the QFP208 package.Test results show that performances of presented classical DSP cases are improved by 28.6%-302%compared with traditional FPGAs.     

一种新型的适用于数字信号处理的FPGA架构研究

本文提出了一种适用于数字信号处理的FPGA结构,该结构能容易的嵌入DSP模块使得在应用于数字信号处理时FPGA的性能得以改善。除了整体结构,本文提出了一种改进的2级多路选择器。 通过在传统2级多路选择器添加SLEEP MODE路径,降低了其静态功耗。此外,本文在长线中途驱动处添加了缓冲器, 使得长线的延迟降低了9.8%,而面积只增加了4.7%。该结构已经成功流片,采用的是标准的0.13um工艺,裸片面积为6.3 × 4.5mm2,采用QFP208封装。与传统FPGA相比,常用DSP模块测试例子的性能提高了28.6% ~ 302%     

Effect of charge sharing on the single event transient response of CMOS logic gates

This paper presents three new types of pulse quenching mechanism(NMOS-to-PMOS,PMOS-to-NMOS and NMOS-to-NMOS) and verifies them using 3-D TCAD mixed mode simulations at the 90 nm node. The three major contributions of this paper are:(1) with the exception of PMOS-to-PMOS,pulse quenching is also prominent for PMOS-to-NMOS and NMOS-to-NMOS in a 90 nm process.(2) Pulse quenching in general correlates weakly with ion LET,but strongly with incident angle and layout style(i.e.spacing between transistors and n-well contact area).(3) Compact layout and cascaded inverting stages can be utilized to promote SET pulse quenching in combinatorial circuits.