脊髓血管畸形血管内栓塞治疗

目的探讨经血管内治疗脊髓动静脉畸形(AVM)的方法.方法本组41例脊髓AVM.3例用3个0真丝线段栓塞,14例采用干燥硬脑膜栓塞,16例采用PVA栓塞,8例采用α-氰基丙烯酸正丁酯(NBCA)胶粘合剂经微导管超选择性栓塞.结果病灶完全栓塞27例,部分栓塞14例,肢体瘫痪症状改善36例,其中5例症状未改善.平均随访32个月,有18例症状完全恢复正常,5例复发,无再出血发生.结论血管内栓塞是治疗脊髓血管畸形的有效方法.     

应用三测定子法测量直齿轮周节累积误差的实验研究

应有和三测定子法测量直齿轮的ｓ个调节误差，并结合理论分析计算，可得到相应的周节累积误差，并得出如下结论：Ｓ个周节误差和周节累积误差与齿轮轮齿表面的加工精度有关；随着周节数的增大，Ｓ个周节误差与周节累积误差的变化范围也大。三测定子法是方便可行的，且比二测定子法更为有效。     

频率量转换数字量的集成电路设计技术

传感器在各领域有着广泛应用,为了测试传感器输出的频率值,在传感器与计算机之间需要一种可以将频率量转换为数字量的专用集成电路。介绍了输出为频率量的传感器测试基本原理,设计了基于这种传感器而研制的专用集成电路,介绍了其电路功能,电路逻辑结构,电路核心器件逻辑设计及功能验证。     

Prevention from Soft Errors via Architecture Elasticity

Due to the decreasing threshold voltages, shrinking feature size, as well as the exponential growth of on-chip transistors, modern processors are increasingly vulnerable to soft errors. However, traditional mechanisms of soft error mitigation take actions to deal with soft errors only after they have been detected. Instead of the passive responses, this paper proposes a novel mechanism which proactively prevents from the occurrence of soft errors via architecture elasticity. In the light of a predictive model, we adapt the processor architectures h01istically and dynamically. The predictive model provides the ability to quickly and accurately predict the simulation target across different program execution phases on any architecture configurations by leveraging an artificial neural network model. Experimental results on SPEC CPU 2000 benchmarks show that our method inherently reduces the soft error rate by 33.2% and improves the energy efficiency by 18.3% as compared with the static configuration processor.     

An Elastic Architecture Adaptable to Various Application Scenarios

The quantity of computer applications is increasing dramatically as the computer industry prospers. Meanwhile, even for one application, it has different requirements of performance and power in different scenarios. Although various processors with different architectures emerge to fit for the various applications in different scenarios, it is impossible to design a dedicated processor to meet all the requirements. Furthermore, dealing with uncertain processors significantly aggravates the burden of programmers and system integrators to achieve specific performance/power. In this paper, we propose elastic architecture （EA） to provide a uniform computing platform with high elasticity, i.e., the ratio of worst-case to best-case performance/power/performance-power trade-off, which can meet different requirements for different applications. It is achieved by dynamically adjusting architecture parameters （instruction set, branch predictor, data path, memory hierarchy, concurrency, status~zcontrol, and so on） on demand. The elasticity of our prototype implementation of EA, as Sim-EA, ranges from 3.31 to 14.34, with 5.41 in arithmetic average, for SPEC CPU2000 benchmark suites, which provides great flexibility to fulfill the different performance and power requirements in different scenarios. Moreover, Sim-EA can reduce the EDP （energy-delay product） for 31.14% in arithmetic average compared with a baseline fixed architecture. Besides, some subsequent experiments indicate a negative correlation between application intervals＇ lengths and their elasticities.     

木塑复合材料的研究开发进展

近年来，木塑材料以其优越的性能越来越得到广泛的应用，本文对木塑材料在国内外研究现状，木塑材料的种类和加工助剂、加工条件、机械等方面进行了简单的介绍。     

基于多模态图像融合的早期蕈样肉芽肿识别

早期蕈样肉芽肿（Mycosis fungoid, MF）可表现为红斑鳞屑性皮损,很难从银屑病及慢性湿疹等良性炎症性皮肤病中鉴别出来。本文提出了一种基于多模态图像融合的早期蕈样肉芽肿识别方法。该方法基于皮肤镜图像和临床图像,采用ResNet18网络提取单模态图像的特征;设计跨模态的注意力模块,实现两种模态图像的特征融合;并且设计自注意力模块提取融合特征中的关键信息,改善信息冗余,从而提高蕈样肉芽肿智能识别的准确度。实验结果表明,本文所提出的智能诊断模型优于对比算法。将本文模型应用于皮肤科医生的实际临床诊断,通过实验组医生和对照组医生平均诊断准确率的变化证实了本文模型能够有效提升临床诊断水平。     

An FFT Performance Model for Optimizing General-Purpose Processor Architecture

General-purpose processor (GPP) is an important platform for fast Fourier transform (FFT),due to its flexibility,reliability and practicality.FFT is a representative application intensive in both computation and memory access,optimizing the FFT performance of a GPP also benefits the performances of many other applications.To facilitate the analysis of FFT,this paper proposes a theoretical model of the FFT processing.The model gives out a tight lower bound of the runtime of FFT on a GPP,and guides the architecture optimization for GPP as well.Based on the model,two theorems on optimization of architecture parameters are deduced,which refer to the lower bounds of register number and memory bandwidth.Experimental results on different processor architectures (including Intel Core i7 and Godson-3B) validate the performance model.The above investigations were adopted in the development of Godson-3B,which is an industrial GPP.The optimization techniques deduced from our performance model improve the FFT performance by about 40%,while incurring only 0.8% additional area cost.Consequently,Godson-3B solves the 1024-point single-precision complex FFT in 0.368 μs with about 40 Watt power consumption,and has the highest performance-per-watt in complex FFT among processors as far as we know.This work could benefit optimization of other GPPs as well.