Space-charge layer capacitance and offset voltage of an exponential-constant p-n junction

It is important to study an exponential-constant p-n junction because it gives a realistic approximation for many diffused p-n junction profiles. To calculate the space-charge layer capacitance for this junction we use an abrupt space-charge edge approximation with a correction which includes the effect of the mobile carriers at the edges of the space-charge region. In this approach the offset voltage v_off is used in place of the built-in potential as obtained from the depletion approximation. An analytical model for the space-charge region capacitance for an exponential-constant junction is developed. This model holds well for zero bias, for small forward voltages, and for reverse voltages. It shows good agreement when compared with the Chawla-Gummel model. It is simple and gives a direct relationship between the depletion capacitance and the applied voltage.     

A Field Guide to Radical Post-Modernism

Sean Griffiths, Charles Holland and Sam Jacob of FAT curate and classify the work of a diverse and international grouping of Radical Post-Modern architects. They range from the recently defunct Foreign Office Architects (FOA), known for their proclivity for pattern and ornament, to Tokyo-based Atelier Bow-Wow who are rigorous in their pursuit of the ordinary. They run the gamut of the highly figurative, as exemplified by Melbourne-based practice ARM, to the expressive austerity of Swiss architect Valerio Olgiati. Copyright © 2011 John Wiley & Sons, Ltd.     

METAL-FERROELECTRIC-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR NAND GATE SWITCHING TIME ANALYSIS

ABSTRACT

Previous research investigated the modeling of a NAND gate constructed of n-channel Metal-Ferroelectric-Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate.     

DESIGN OF A MULTI-LEVEL/ANALOG FERROELECTRIC MEMORY DEVICE

ABSTRACT

Increasing the memory density and utilizing the novel characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.