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A single die 1.2 V multi-stage noise shaping(Mash) 2-2 delta sigma analog to digital converter(ADC)for wide applications is implemented. The configurable Mash 2-2 modulator with a new decimation filter design is presented to achieve wide and high dynamic range(DR) for multiple practical applications. The novel modulator can be configured as a Mash 2-2 modulator for high precision or a 2-order modulator for low DR. The decimation filter is designed to select the OSR flexibly among cascaded integrator comb(CIC) filter and two half-band filters(HBF). The serial peripheral interface(SPI) can be used to adjust the sampling frequency and the oversampling ratio(OSR). The design was fabricated in a 0.13 m CMOS process with an area of 0.91 mm2and a total power of 5.2 mW. The measurement results show that the dynamic range(DR) of the proposed ADC can change from 55to 95 dB with the configurable OSR from 16 to 256. The spurious free dynamic range(SFDR) and signal-to-noise distortion ratio(SNDR) can get 99 dB and 86.5 dB, respectively. 相似文献
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A CMOS long-term evolution(LTE) direct convert receiver that eliminates the interstage SAW filter is presented.The receiver consists of a low noise variable gain transconductance amplifier(TCA),a quadrature passive current commutating mixer with a 25%duty-cycle LO,a trans-impedance amplifier(TIA),a 7th-order Chebyshev filter and programmable gain amplifiers(PGAs).A wide dynamic gain range is allocated in the RF and analog parts.A current commutating passive mixer with a 25%duty-cycle LO improves gain,noise,and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference.Fabricated in a 0.13μm CMOS process,the receiver chain achieves a 107 dB maximum voltage gain,2.7 dB DSB NF(from PAD port),-11 dBm 11P3,and>+65 dBm UP2 after calibration,96 dB dynamic control range with 1 dB steps,less than 2%error vector magnitude(EVM) from 2.3 to 2.7 GHz.The total receiver(total I Q path) draws 89 mA from a 1.2-V LDO on chip supply. 相似文献
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本文提出了一种应用于LTE直接变频接收机的CMOS射频前端电路。电路由低噪声跨导放大器(LNA),电流型无源混频器和跨阻运算放大器(TIA)组成,该结构对于LTE多频带应用具有高集成,高线性,并实现简单的频率配置。电路采用多个电流舵跨导级实现了大的可变增益控制范围。电流型无源混频器采用25%占空比本振改善了电路增益、噪声和线性性能。为了抑制带外干扰,采用直接耦合电流输入滤波器。该射频前端电路采用0.13-μm CMOS工艺设计制造。测试结果表明电路在2.3GHz到2.7GHz工作频率范围,具有45dB电压转换增益,噪声系数为2.7dB,IIP3为-7dBm以及校准后的IIP2为 60dBm。电路采用1.2V单电压供电,整个电路工作电流为40mA。 相似文献
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In order to improve the performance of the dye-sensitized solar cells based on ZnO films, ZnO nanoparticles of different sizes were prepared by two methods. Some surfactants were added into the particles to form three types of ZnO pastes. Electrodes of various thickness applied to dye-sensitized solar cell were prepared starting from each of those pastes by the screen-printing method. The performance of dye-sensitized solar cells was optimized via both the selected particle size and film thickness. The reason of the inefficiency was explained by the infrared and ultraviolet- visible absorption spectra. 相似文献
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一种具有自适应节能的新型4/5高速双模预分频器 总被引:1,自引:1,他引:0
首次提出一种自适应节能方法用于设计4/5高速双模预分频器,它的特点是工作在除4模式时,其中一个D类触发器处于休眠状态.使用台积电混合信号0.25μm CMOS工艺,采用这一自适应节能的设计方法,设计了一个具有源极耦合结构的4/5高速舣模预分频器.仿真结果证明,这一新型4/5高速双模预分频器不受休眠到工作转换状态的影响,最高工作频率保持不变.同时,流片结果表明,当这一新型高速预分频器用于实现66/67分频时,可节省高达20%以上的功耗. 相似文献
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