Parallel architecture for fast transforms with trigonometric kernel

We present an unified parallel architecture for four of the most important fast orthogonal transforms with trigonometric kernel: Complex Valued Fourier (CFFT), Real Valued Fourier (RFFT), Hartley (FHT), and Cosine (FCT). Out of these, only the CFFT has a data flow coinciding with the one generated by the successive doubling method, which can be transformed on a constant geometry flow using perfect unshuffle or shuffle permutations. The other three require some type of hardware modification to guarantee the constant geometry of the successive doubling method. We have defined a generalized processing section (PS), based on a circular CORDIC rotator, for the four transforms. This PS section permits the evaluation of the CFFT and FCT transforms in n data recirculations and the RFFT and FHT transforms in n-1 data recirculations, with n being the number of stages of a transform of length N=rⁿ. Also, the efficiency of the partitioned parallel architecture is optimum because there is no cycle loss in the systolic computation of all the butterflies for each of the four transforms     

Algorithm for cosine transform of Toeplitz matrices

An algorithm for calculating the 2D cosine transform of a Toeplitz matrix is presented. The algorithm is based on the application of 1D cosine transforms. More specifically, four 1D cosine transforms of size N are needed to obtain the transform of a Toeplitz matrix of size N×N. This is an improvement over previously published algorithms. The algorithm is also simple and regular     

Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures

A rate 1/n binary generic convolutional encoder is a shift-register circuit where the inputs are information bits and the outputs are blocks of n bits generated as linear combinations on the appropriate shift register contents. The decoding of the outputs of a convolutional encoder can be carried out by the well-known Viterbi algorithm. The communication pattern of the Viterbi Algorithm is given as a graph, called trellis, associated to the state diagram of the corresponding encoder. In this paper we present a methodology that permits the efficient mapping of the Viterbi algorithm onto a column of an arbitrary number of processors. This is done through the representation of the data flow by using mathematical operators which present an inmediate hardware projection. A single operator string has been obtained to represent a generic encoder through the study of the data flow of free-forward encoders and feed-back encoders. The formal model developed is employed for the partitioning of the computations among an arbitrary number of processors in such a way that the data are recirculated opimizing the use of the processors and the communications. As a result, we obtain a highly regular and modular architecture suitable for VLSI implementation.     

Diode-Pumped Solid-State Lasers for Inertial Fusion Energy

We have begun building the Mercury laser system as the first in a series of new generation diode-pumped solid-state lasers for inertial fusion research. Mercury will integrate three key technologies: diodes, crystals, and gas cooling, within a unique laser architecture that is scalable to kilojoule and megajoule energy levels for fusion energy applications. The primary near-term performance goals include 10% electrical efficiencies at 10 Hz and 100J with a 2–10 ns pulse length at 1.047 m wavelength. When completed, Mercury will allow rep-rated target experiments with multiple chambers for high energy density physics research.     

Resilient overlay network for real-time interactive multimedia sessions in corporate networks

Real-time interactive multimedia communications are becoming increasingly useful for education, business, e-commerce and e-government, providing an enriched user experience in teleconferencing, e-meetings, distance training and product demonstrations. Large corporations are usually located at several sites, so real-time multipoint sessions within corporations are especially difficult. IP multicast is available or feasible within each site of an organization. Thus, corporate networks can be considered as various multicast-capable networks interconnected through a wide area network without multicast connectivity. This paper proposes a resilient self-managed overlay network to support real-time multipoint interactive sessions within corporate networks. The proposed overlay takes advantage of the configuration of corporate networks to self-organize and provide an efficient media delivery service, making use of multicast communications wherever available. Various self-healing techniques are implemented allowing for the continuity of ongoing sessions in spite of network disruptions and entity failures. Extensive simulations and tests have been carried out to assess the performance and resilience of the overlay facing several types of disruptions.     

Current-mode analogue defuzzifier

A CMOS current-mode approach for implementing the defuzzification function in analogue fuzzy controllers is proposed. The circuit computes the centre of area of the output fuzzy conclusion using switched current adders and a current divider. Simulation results of the defuzzifier show how the circuit can produce a good approximation of the centre of area even if a small number of levels are used to quantise the output variable.<>     

A CAD-oriented method to analyze and design radiating structures based on bodies of revolution by using finite elements and generalized scattering matrix

In this work, an efficient analysis of radiating structures based on bodies of revolution is dealt with. The procedure is a hybrid method based on a segmentation of the structure into two-dimensional regions, finite elements and a spherical computation domain surrounding the antenna, defining a boundary or port where a spherical mode expansion of the fields is used. A reduced order model is computed for a fast frequency sweep. To validate this method, some structures based on bodies of revolution as a rod dielectric antenna, conical dielectric-loaded horns, profiled horns and a monopole-dielectric resonator antenna are studied and results are compared with those demonstrated by other authors. The design of a smooth-walled horn by means of the optimization of the profile is also carried out.     

An energy efficient middleware for an ad-hoc AAL wireless sensor network

DIA (Dispositivo Inteligente de Alarma, in Spanish) is an AAL (Ambient Assisted Living) system that allows to infer a potential dangerous action of an elderly person living alone at home. This inference is obtained by a specific sensorisation with sensor nodes (portables and fixes) and a reasoning layer embedded in a PC that learns of the users behaviour patterns and advices when actual one differs significantly of the normal patterns. In AAL systems, energy is a limited resource therefore sensor devices need to be properly managed to conserve energy. In this paper, we introduce the design and implementation of innovative and specific mechanisms at the sensory layer middleware which is capable of, first to discriminate spurious motion detections assuming that these signals do not resemble the patterns of real motion detections and, second to reduce the dynamics of messages by a sensor signal processing in order to compress the whole information in one single event. The middleware achieves power saving by modifying the raw information from sensors and adapting it to the predefined semantic of the reasoning layer. It manages the important task of data processing from sensors (raw information), and transfers the pre-processed information into the top layer of reasoning in a more energy efficient way. We also address the trade-off between reducing power consumption and reducing delay for incoming data. We present results from experiments using our implementation of these mechanisms at the middleware that comprises from node firmware to the PC driver. The number of messages of the proposed method with respect to the raw data is reduced by approximately 98.5%. The resources used in the PIR signal processing is reduced by approximately 85%. The resulting delay introduced is small (10–19 s) but system dynamics is slow enough to avoid contextualisation errors or reduction of system performance. We consider these results as very satisfactory.     

Radix-4 Vectoring CORDIC Algorithm and Architectures

In this work we extend the radix-4 CORDIC algorithm to the vectoring mode (the radix-4 CORDIC algorithm was proposed recently by the authors for the rotation mode). The extension to the vectoring mode is not straightforward, since the digit selection function is more complex in the vectoring case than in the rotation case; as in the rotation mode, the scale factor is not constant. Although the radix-4 CORDIC algorithm in vectoring mode has a similar recurrence as the radix-4 division algorithm, there are specific issues concerning the vectoring algorithm that demand dedicated study. We present the digit selection for nonredundant and redundant arithmetic (following two different approaches: arithmetic comparisons and table look-up), the computation and compensation of the scale factor, and the implementation of the algorithm (with both types of digit selection) in a word-serial architecture. When compared with conventional radix-2 (redundant and non-redundant) architectures, the radix-4 algorithms present a significant speed up for angle calculation. For the computation of the magnitude the speed up is very slight, due to the nonconstant scale factor in the radix-4 algorithm.