Suggestions to the article: medical professionalism research characteristics and hotspots

Scientometrics - The article published on 5 July 2021 is well-written and of interest. However, some improvements could be made, such as ten Tables/Figures can be shortened to highlight the focused...     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.     

The Synthesis of Sulfated Titanium Oxide Nanotubes

TiO₂ nanotubes can be prepared in gram quantities by treating anatase TiO₂ powder with concentrated NaOH solution. These TiO₂ nanotubes acquired strong acidity after being impregnated with sulfuric acid solution and calcined at 300 °C. The anatase TiO₂ powder used to prepare the nanotube did not catalyze the esterification between cyclohexanol and acetic acid, while sulfated TiO₂ nanotubes were very reactive toward the esterification reaction.     

Experimental determination of NH<Subscript>4</Subscript>NO<Subscript>3</Subscript>-KNO<Subscript>3</Subscript> binary phase diagram

The solid-state phase transitions in ammonium nitrate (AN)-potassium nitrate (KN) system, and the equilibrium AN-KN phase diagram have been determined by using differential scanning calorimetry and high-temperature in situ x-ray diffractometry. Sample preparation was performed in a special “dry room” with very low humidity. A single phase region (AN III) with no phase transitions to 373 K was observed in the composition range 5 to 20% KN; this is critical for use in air bag gas generators. The high-temperature KN phase (KN I) has a wide range of stability from 20 to 100 wt.% KN. There are one eutectic, two eutectoid, three peritectoid, and one congruent transformations in this phase diagram. Two new nonstoichiometric phases were found at lower temperatures in the mid-composition range between the AN and KN terminal solid solutions. Details of the phase equilibria are presented.     

Optimum power-saving method for power MOSFET width of DC/DC converters

An optimum power metal-oxide-semiconductor field effect transistor (MOSFET) width technique is proposed for enhancing the efficiency characteristics of switching DC-DC converters. By implementing a one-cycle buck DC-DC converter, it is demonstrated that the dynamic power MOSFET width controlling technique has a much improved power reduction whether the load current is light or heavy. The maximum efficiency of the buck converter is ~92% with a 3% efficiency improvement for the heavy load condition. The efficiency is further improved by ~16% for the light load condition as a result of the power reduction from the large power MOSFET transistors. Also proposed is a new error-correction loop circuit to enable a better load regulation than that of previous designs. Compared with the adaptive gate driver voltage technique, the optimum power MOSFET width can achieve a significant improvement in power saving. It is also superior to the low-voltage-swing MOSFET gate drive technique for switching DC-DC converters