An epidemiologic, clinical, and therapeutic study of childhood Guillain-Barré syndrome in Kuwait: is it related to the oral polio vaccine?

We studied Guillain-Barré syndrome, affecting children 12 years old or less, throughout Kuwait, in the period between January 1, 1992, and March 31, 1997. Nineteen children had the diagnostic criteria of Guillain-Barré syndrome, with an overall annual incidence rate of 0.95/100,000 population at risk. Female patients outnumbered male patients with a sex ratio of 1.4:1. There was a clustering of cases in winter and spring and in the year 1996. The disease symptoms were relatively severe in our patients because only 16% (3 of 19) of them were able to walk at the height of their illness, whereas the rest were bed or chair bound or needed assisted ventilation. Two patients had the electrodiagnostic features of axonal neuropathy and both had residual deficits on follow-up, whereas the rest recovered fully. All the patients received intravenous immunoglobulin. The mean time to walk unaided was 23.5 days (range, 2-84 days) after intravenous immunoglobulin and excluding the two patients with axonal neuropathy, and full recovery was achieved in a mean time of 103 days (range, 30-300 days). Contrary to previous studies, we found no correlation between oral polio vaccine administration and Guillain-Barré syndrome in 2 successive years (1995 and 1996) during a nationwide campaign targeting children less than 5 years old.     

High speed p-type SiGe modulation-doped field-effect transistors

We report on the fabrication and characterization of high-speed p-type modulation-doped field-effect transistors (MODFETs) with 0.7-μm and 1-μm gate-lengths having unity current-gain cut-off frequencies (f_T) of 9.5 GHz and 5.3 GHz, respectively. The devices were fabricated on a high hole mobility SiGe heterostructure grown by ultra-high-vacuum chemical vapor deposition (UHV-CVD). The dc maximum extrinsic transconductance (g_m) is 105 mS/mm (205 mS/mm) at room temperature (77 K) for the 0.7-μm gate length devices. The fabricated devices show good pinch-off characteristics and have a very low gate leakage current of a few μA/mm at room temperature and a few nA/mm at 77 K     

High performance analog VLSI computational circuits

Simple linear voltage/current-controlled voltage-to-current (V-T) converters, which are to first-order insensitive to the threshold voltage variation, are introduced. The circuits can be used as basic building blocks to construct simple analog computational circuits, which can perform functions such as square rooting, squaring, multiplication, sum of squares, difference of squares, etc. Some of the key features are: good linearity, floating inputs [high common-mode rejection ratio (CMRR)], simplicity, and good transconductance tuning range. The circuits can be realized with CMOS devices in saturation, however, BiCMOS devices extend their speed and input voltage range. Realistic simulations and experimental results clearly demonstrate the claims     

Link budget analysis for multistandard receiver architectures

As devices shrink, creating integrated circuits (ICs) that work with the required accuracy becomes more difficult due to issues related to device physics. Receivers are part of an area referred to as "mixed-signal design," meaning that both analog and digital circuitry will be on the same IC. This too presents many challenging issues, as the analog circuitry is highly sensitive to disruptions caused by the noisy digital circuitry. Therefore, accurate modeling and simulation is crucial in the design of wireless receivers to ensure the best possible operation of the fabricated IC. Through simulation and modeling a designer can determine if receiver architecture will meet the required specifications and pinpoint the possible problems before valuable time is spent developing the actual circuit. This article will present design issues for multistandard wireless receivers to give the reader an understanding of the challenges involved in link-budget analysis. TITAN (Toolbox for Integrated Transceiver Analysis), a link-budget analysis tool developed at The Ohio State University Analog VLSI Laboratory, will be presented as an example of a tool for receiver simulation. To determine design performance, various requirements must be translated to model parameters. Among the requirements for receivers are noise floor (NF), second- and third-order distortion (IP2 and IP3, respectively), reciprocal mixing, and phase noise. TITAN offers a graphical interface and encapsulated models to the designer, eliminating the possibility of formula corruption. The interface provides a more intuitive and sophisticated way of setting up the simulation and provides the designer with more readable results. Additionally, a blocking profile component allows the architecture to be tested across multiple standards.     

Rapid determination of the fracture toughness of metallic materials using circumferentially notched bars

Three types of material whose fracture toughness tests were previously performed by using circumferentially notched bars, namely (1) a dual-phase steel with three different morphologies; (2) an Al-Zn-Mg-Cu-wrought alloy; and (3) Al-Si-cast alloys with three different Si contents, were investigated in terms of accuracy and reliability of the testing method. Also, the advantages of using circumferentially notched bars for fracture toughness determination of metallic materials were discussed. With the help of stress concentration factors, which are associated with the bluntness of the notch, correction factors for the fracture toughness calculations are derived. The corrected fracture toughness values are found to be close to the uncorrected ones, implying that the testing procedure is reliable.     

Statistical modeling of device mismatch for analog MOS integratedcircuits

A generalized parameter-level statistical model, called statistical MOS (SMOS), capable of generating statistically significant model decks from intra- and inter-die parameter statistics is described. Calculated model decks preserve the inherent correlations between model parameters while accounting for the dependence of parameter variance on device separation distance and device area. Using a Monte Carlo approach to parameter sampling, circuit output means and standard deviations can be simulated. Incorporated in a CAD environment, these modeling algorithms will provide the analog circuit designer with a method to determine the effect of both circuit layout and device sizing on circuit output variance. Test chips have been fabricated from two different fabrication processes to extract statistical information required by the model. Experimental and simulation results for two analog subcircuits are compared to verify the statistical modeling algorithms