Effects of drying temperature and relative humidity on spaghetti characteristics

This study aimed at investigating the effect of drying conditions on spaghetti properties, i.e., its color, surface structure, rupture strength, rehydration characteristics, texture, and sauce retention capacity. The effects of temperature and humidity were independently examined under constant drying conditions, which were compared to those applied industrially, where the temperature and relative humidity are changed stepwise with time. The knowledge obtained in this study is considered useful for reasonably determining the drying conditions for producing spaghetti with desired properties.     

A 3.84 GIPS integrated memory array processor with 64 processingelements and a 2-Mb SRAM

An integrated memory array processor (IMAP) ULSI with 64 processing elements and a 2-Mb SRAM has been developed for image processing. The chip attains a 3.84 GIPS peak performance through the use of SIMD parallel processing and a 1.28 GByte/s on-chip processor-memory bandwidth. The IMAP is capable of parallel indirect addressing, which increases applications for parallel algorithms. Large power consumption with the wide memory bandwidth is avoided by reducing the number of active sense amplifiers and adopting dynamic power control. Fabricated with a 0.55-μm BiCMOS double layer metal process technology, the IMAP contains 11 million transistors in a 15.1×15.6 mm² die area     

Permethylation alters the conformational transitions and the complexing ability of melittin: a model for methylated proteins

A number of researches have used factor analyses and principal components analyses on handedness questionnaire data in order to learn something about handedness. However, these researchers have analyzed pooled data from righthanders and lefthanders. The practice of pooling groups that are known in advance to be heterogeneous is highly questionable because it is not possible to disentangle the sources of variance that are contributed by within group differences from those that arise from between group differences. The factor structure and item loadings that result from pooled data are misleading and cannot inform meaningfully about the relation of hand preference to handedness. Similar problems can be anticipated in other neuropsychological applications of factor analysis, where data from heterogeneous groups is pooled.     

Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memoryarray processor applications

We have fabricated a high yield integrated memory array processor (IMAP) LSI, which features a high memory bandwidth (1.28-GB/s) and low power consumption (4-W max.) and which contains a 2-Mb SRAM with 1.28-I/O's and 64 processor elements (PE's) in one chip. A high-bandwidth and low-power memory circuit design is the key technology to realize the IMAP-LSI. We adopted following new designs for memory circuit. (1) Memory access time is designed to be twice as fast as PE execution time (2) Employment of dynamic power control mode, which reduces the memory power consumption down to 30% of maximum power without a loss in access-speed (3) Simplified synchronization with PE's (4) 4-way block redundancy. These design techniques are suitable for future system integrated ULSI's     

A case of Sj?gren syndrome associated with multiple mononeuritis and dysautonomia including bilateral tonic pupils

In the present study, the feasibility of intrathecal indwelling catheters in the preparation of a repeated subarachnoid hemorrhage (SAH) model in dogs, as well as chronic intrathecal administration of therapeutic agents against the ensuing cerebral vasospasm was examined. Briefly, through a small suboccipital incision, two catheters were introduced into the subarachnoid space so that their tips were positioned in the prepontine cistern. One was used to induce SAH by infusing autologous blood, and the other to administer pharmacological agents (saline and/or saline containing a dye in this study) by means of an osmotic pump. The occurrence of cerebral vasospasm was followed by angiography via the catheter placed in the vertebral artery. The obtained results show: i) the injected blood effectively formed a subarachnoid clot in the prepontine cistern, invariably leading to the occurrence of severe cerebral vasospasm of the basilar artery; ii) the fluid injected by the osmotic pump was evenly distributed in the cisterns around the brain stem; iii) on post mortem pathological examination, no injury of the brain or the major arteries ascribable to the placement of catheters was found. Therefore, the present model is considered to be useful for both the investigation of pathophysiology and therapy of cerebral vasospasm following SAH, to be more favorable from the standpoint of animal protection, and more convenient and reliable than those used until now.     

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage V/sub DD/ and threshold voltage V/sub TH/ in active and standby modes. In the active mode, on the basis of delay monitoring results, either VDD control or VTH control is selected to avoid any oscillation problem between them. In V/sub DD/ control, on the basis of delay monitoring results, VDD is adjusted so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. In V/sub TH/ control, on the basis of power monitoring results, VTH is adjusted so as to maintain a certain switching current I/sub SW//leakage current I/sub LEAK/ ratio known to indicate minimum power consumption. In the standby mode, the precision of power monitoring (which detects optimum body bias by comparing subthreshold current I/sub SUBTH/ to substrate current I/sub SUB/) is improved by taking into consideration both the effects of lowering V/sub DD/ and the effects of the presence of gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that use of the proposed power monitoring results in the successful minimizing of power consumption. It does so by making it possible to: 1) maintain the I/sub SW//ILEAK ratio in the active mode and 2) detect optimum body bias conditions (I/sub SUBTH/=ISUB) within an error of less than 20% with respect to actual minimum leakage current values in the standby mode.     

An ultrahigh-density high-speed loadless four-transistor SRAM macrowith twisted bitline architecture and triple-well shield

We have developed two schemes for improving access speed and reliability of a loadless four-transistor (LL4T) SRAM cell: a dual-layered twisted bitline scheme, which reduces coupling capacitance between adjacent bitlines in order to achieve highspeed READ/WRITE operations, and a triple-well shield, which protects the memory cell from substrate noise and alpha particles. We incorporated these schemes in a high-performance 0.18-μm-generation CMOS technology and fabricated a 16-Mb SRAM macro with a 2.18-μm² memory cell. The macro size of the LL4T-SRAM is 56 mm², which is 30% to 40% smaller than a conventional six-transistor SRAM when compared with the same access speed. The developed macro functions at 500 MHz and has an access time of 2.0 ns. The standby current has been reduced to 25 μA/Mb with a low-leakage nMOSFET in the memory cell     

Characterization of Spaghetti Prepared Under Different Drying Conditions

Spaghetti dried at low (max. 50 °C), high (max. 70 °C), and very high (max. 85 °C) temperatures were characterized by their color, surface structure, rupture strength, texture analysis, and sauce retention capacity. The texture and sauce retention capacity were estimated for cooked spaghetti. The color of the spaghetti's methanol extracts, as evaluated through absorbance at 440 and 466 nm, did not depend on the drying temperature. A trend was observed in the surface texture of spaghetti, as estimated by atomic force microscopy and mercury intrusion porosimetry, where the surface was rougher when dried at higher temperatures than at low temperatures. Furthermore, the rupture strength was also higher for the spaghetti dried at higher temperatures. This result can be ascribed to the formation of stronger gluten networks, promoted by denaturation of gluten at the higher temperatures. However, the hardness of cooked spaghetti was not affected by the drying temperature, a result attributable to the action of water sorption to offset any differences in hardness among the spaghettis dried at the 3 different temperatures. The sauce retention capacity of cooked spaghetti was evaluated using a dextran solution as a simulated sauce, and by this method, the capacity of the spaghetti dried at a low temperature was shown to be significantly lower than that of the spaghetti dried at higher temperatures. This can be ascribed to the smoother surface of cooked spaghetti dried at the lower temperature and also to the leakage of amylose onto the surface during cooking.     

A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications

To help overcome limits to the speed of conventional SRAMs, we have developed a read-static-noise-margin-free SRAM cell. It consists of seven transistors, several of which are low-Vth nMOS transistors used to achieve both low-VDD and high-speed operations. For the same speed, the area of our proposed SRAM is 23% smaller than that of a conventional SRAM. Further, we have fabricated a 64-kb SRAM macro using 90-nm CMOS technology and have obtained with it a minimum VDD of 440 mV and a 20-ns access time with a 0.5-V supply.     

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 64-Mb dynamic random access memory (DRAM) with a 30-ns access time and 19.48-mm×9.55-mm die size has been developed. For reducing inter-bit-line coupling noise, the DRAM features a latched-sense, shared-sense circuit with open bit-line readout and folded bit-line rewrite operations. To reduce test costs and increase chip reliability, it has been equipped with built-in self-test and self-repair (BIST and BISR) circuits that use spare SRAM cells