一款14位250MS/s采样率的电流舵数模转换器

A 14-bit 250-MS/s current-steering digital-to-analog converter(DAC) was fabricated in a 0.13μm CMOS process.In conventional high-speed current-steering DACs,the spurious-free dynamic range(SFDR) is limited by nonlinear distortions in the code-dependent switching glitches.In this paper,the bottleneck is mitigated by the time-relaxed interleaving digital-random-return-to-zero(TRI-DRRZ).Under 250-MS/s sampling rate,the measured SFDR is 86.2 dB at 5.5-MHz signal frequency and 77.8 dB up to 122 MHz.The DAC occupies an active area of 1.58 mm2 and consumes 226 mW from a mixed power supply of 1.2/2.5 V.     

黑曲霉α-L-鼠李糖苷酶与柚皮苷分子动力模拟研究

L-鼠李糖苷酶能够水解柚皮苷生产普鲁宁和L-鼠李糖,可用于柑橘类果汁的脱苦处理。对柚皮苷和黑曲霉α-L-鼠李糖苷酶进行分子对接,采用分子动力模拟和MM-PBSA结合的方法计算对接复合物的结合自由能,并分析了分子间相互作用以及各个残基对结合自由能的贡献。结果表明范德华作用力是黑曲霉α-L-鼠李糖苷酶与柚皮苷结合的主要驱动力,库伦电荷作用和非极性溶剂化能对结合贡献较小。Trp236、Ala340、Ile462、Phe461、Tyr516、Val522、Trp528等是黑曲霉α-L-鼠李糖苷酶和柚皮苷结合过程中形成疏水作用的重要氨基酸残基。在分子动力模拟平衡后的氢键分析中,黑曲霉α-L-鼠李糖苷酶Ser286、Phe465、Pro520残基和柚皮苷共形成了3个稳定的氢键。本研究分析了黑曲霉α-L-鼠李糖苷酶与柚皮苷结合的驱动力,以及结合过程中重要氢键及疏水性残基,为蛋白质工程改造α-L-鼠李糖苷酶提供了靶位。     

α-L-鼠李糖苷酶高密度发酵及其固定化

在5 L发酵罐中对α-L-鼠李糖苷酶进行小试发酵,制备酶液;以聚乙烯醇-海藻酸钠为包埋载体,以戊二醛为交联剂对该酶进行固定化。经5 L罐高密度发酵96 h,α-L-鼠李糖苷酶酶活为2 766 U/g,生物量为228g/L。经过固定化后,α-L-鼠李糖苷酶的酶活为20 U/g,酶活回收率为32.88%,固定化α-L-鼠李糖苷酶的最适反应温度为35~50℃,最适反应p H值为4.0,该固定化酶在连续使用6次后酶活仍然保留98.22%。高密度发酵能显著提高酶的产量,同时固定化技术提高了酶的重复利用率,为该酶利用芦丁酶法转化制备异槲皮苷提供了依据。     

多点突变提高α-L-鼠李糖苷酶热稳定性

为了提高α-L-鼠李糖苷酶的热稳定性,对实验室前期构建的K406R、K440R、K573V、E631F四个不同氨基酸位点的单点突变体进行联合突变,得到了K406R-K573V、K406R-E631F、K440R-K573V、K440R-E631F四个联合突变体。结果表明,相比于野生型(wild type,WT),联合突变体K440R-K573V和K440R-E631F的热稳定性有所提高,在60℃时半衰期分别提高了1. 13倍,1. 44倍;在65℃的半衰期分别提高了1. 64倍,1. 64倍;在70℃的半衰期分别提高了1. 88倍,1. 68倍。对突变体K440R-E631F进行圆二色谱分析、分子动力学以及分析微观结构变化分析可知,K440R-E631F突变体与WT相比,内部疏水性有所提高,二级结构中α-螺旋、"-转角、无规则卷曲含量增多,可能与热稳定性的提高相关。     

一种基于数字后台校准技术的14 bit 500 MS/s 数模转换器

Thelinearityofcurrent-steeringdigital-to-analogconverters（DACs）atlowsignalfrequenciesismainly limited by matching properties of current sources, so large-size current source arrays are widely used for better matching. This, however, results in large gradient errors and parasitic capacitance, which degrade the spurious free dynamic range（SFDR） for high-frequency signals. To overcome this problem, calibration is an effective method.In this paper, a digital background calibration technique for current-steering DACs is presented and verified by a 14-bit DAC in a 0.13 m standard CMOS process. The measured differential nonlinearity（DNL） and integral nonlinearity（INL） are 0.4 LSB and 1.2 LSB, respectively. At 500-MS/s, the SFDR is 70 dB and 50.3 dB for signals of 5.4 MHz and 224 MHz, respectively. The core area is 0.69 mm2and the power consumption is 165 mW from a mixed power supply with 1.2 V and 3.3 V.