一个单通道10位160兆每秒的逐次逼近式模数转换器

This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register （SAR） analog-to-digital converter （ADC） in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied.     

低中频GPS接收机中低通滤波器的设计与实现

采用SMIC0．18μm工艺,实现了一个截止频率可调谐,带品质因数（Q值）补偿的五阶巴特沃兹低通滤波器,截止频率在9MHz,50MHz处抑制在70dB以上,通带增益变化在0．3dB以内,面积0．4mm^2,功耗12mW。此低通滤波器已经成功地应用在GPS低中频接收机中。