MOS VLSI数字电路分区间时延建模方法

<正> 一、引言 时延模型是逻辑模拟、开关级模拟、定时模拟以及定时分析与验证中的基本问题。目前时延模型大多为经验式的。其分析结果与实际电路时延相差很大。实际电路时延特性的复杂性是造成这种情况的主要原因,晶体管尺寸、阈值电压、基元互联、负载电容、输入波形,以及晶体管在电路中的使用方式等因素都将影响电路的时延。 本文在作者近来工作的基础上,提出了基于时延势概念的一种理论上自洽的时延建模方法,所得模型简单,精度较以往时延模型提高,从而为节点时延势方程理论的实用化奠定了基础。     

具有动态模式控制和斜波补偿的宽负载、多模式同步降压DC-DC转换器

A synchronous buck DC-DC converter with an adaptive multi-mode controller is proposed.In order to achieve high efficiency over its entire load range,pulse-width modulation(PWM),pulse-skip modulation(PSM) and pulse-frequency modulation(PFM) modes were integrated in the proposed DC-DC converter.With a highly accurate current sensor and a dynamic mode controller on chip,the converter can dynamically change among PWM, PSM and PFM control according to the load requirements.In addition,to avoid power device damage caused by inrush current at the start up state,a soft-start circuit is presented to suppress the inrush current.Furthermore,an adaptive slope compensation(SC) technique is proposed to stabilize the current programmed PWM controller for duty cycle passes over 50%,and improve the degraded load capability due to traditional slope compensation.The buck converter chip was simulated and manufactured under a 0.35μm standard CMOS process.Experimental results show that the chip can achieve 79%to 91%efficiency over the load range of 0.1 to 1000 mA.     

用于开关DC-DC变换器的高精度片上电流检测电路

设计了一种应用于开关DC-DC变换器的高精度片上电流检测电路。与传统方法相比,该电流检测方式采用无运算放大器的结构,去除了无运算放大器结构中的电流共享,从而提高了电流检测精度。将该电流检测电路应用于一款同步降压型DC-DC变换器,芯片采用0.35μm标准CMOS工艺。实验结果显示,电流检测精度在轻负载时可达98.7%,在大负载时高达99.7%。