湖北省电子设计竞赛一等奖 调幅发射机电路的设计(A题)

简易调幅发射机,由调幅信号源和高频高效功率放大器组成。调幅信号源由LC振荡电路产生正弦波;锁相环芯片MC145152和双模分频器MC12017组成锁相环,将载波频率精确的锁定在15MHz,输出载波的稳定度和准确度达到2×10-6;振幅调制采用MC1496,调制度固定为30%,输出幅度调节范围宽;高频功率放大级应用功率合成技术,采用反相推挽功率合成电路,在50Ω负载上输出功率大于60mW。本设计有功率和效率数字显示,负载电压和功放电源电压、电流经A/D,由单片机计算出输出功率和效率,128×64液晶LCD显示。整个设计的优点在于频率稳定度和准确度高、调制度稳定在30%,输出功率大、效率高。     

基于GaAs HBT工艺的3.8GHz带宽4GS/s 4bit超高速ADC

报道了一种4GS/s 4bit超宽带（UWB）模数转换器（ADC）芯片,采用1.4um发射级宽度、2层金属布线的InGaP/GaAs HBT工艺实现。该芯片采用折叠内插架构来最小化其面积和电路规模。为了消除折叠内插电路中的偶发错误码,该ADC采用了一种新颖的比特同步电路。实测结果表明,其在4GS/s采样率下具有3.8GHz的模拟带宽和2.6GHz的有效精度带宽（ERBW）,在2.6GHz输入带宽内ADC的有效位数大于3.4bit,在4GHz输入带宽内有效位大于3bit。在6.001GHz输入并将输入功率提高4dB后,有效位仍然高达3.49bit,表明该ADC可采样的频率范围包含从第一到第三奈奎斯特区（DC~6GHz）。该芯片的DNL和INL在4GS/s下均小于±0.15LSB,总面积为1.45×1.45 mm2,总功耗为1.98W。     

A 10 GHz high-efficiency and low phase-noise negative-resistance oscillator optimized with a virtual loop model

A virtual loop model was built by the transmission analysis with virtual ground method to assist the negative-resistance oscillator design, providing more perspectives on output power and phase-noise optimization. In this work, the virtual loop described the original circuit successfully and the optimizations were effective. A 10 GHz high-efficiency low phase-noise oscillator utilizing an InGaP/GaAs HBT was achieved. The 10.028 GHz oscillator delivered an output power of over 15 dBm with a phase-noise of lower than -107 dBc/Hz at 100 kHz offset. The efficiency of DC to RF transformation was 35 %. The results led to a good oscillator figure of merit of-188 dBc/Hz. The measurement results agreed well with those of the simulations.     

一种用于直接射频采样ADC的多模式数字下变频器设计

为满足直接射频采样ADC对数字下变频器（DDC）抽取模式数量的需求,提出了一种多模式DDC设计。文章首先研究和分析了AD采样原理、DDC原理和高速高精度数控振荡器原理,建立了基于多模式抽取滤波器组的DDC模型,并进行了行为级仿真和分析,之后采用Verilog HDL完成了RTL设计与仿真,利用Synopsys数字后端工具链完成了基于28nm的版图设计与后仿。仿真显示,该设计可工作在1GHz时钟下,实现了14种模式,最低阻带衰减大于100dB,在抽取系数为2的条件下,-3dB带宽达到478.867MHz。包含ADC所需的其他数字电路的总面积为1300um * 1370um（DDC约占67%）,总仿真功耗为301.7mW。该设计具有抽取模式多、功耗低、消耗资源少的优点,能够满足直接射频采样ADC对多模式DDC的需求。     

75 GHz 13.92 dBm InP DHBT 共射共基功率放大器

报道了基于InP基双屏质结双板晶体管(DHBT)工艺的四指共射共基75 GHz微波单片集成(MMIC)功率放大器,器件的最高振荡频率fmax为150 GHz.放大器的输出极发射极面积为15μm×4μm.功率放大器在75 GHz时功率增益为12.3 dB,饱和输出功率为13.92 dBm.放大器在72.5 GHz处输入为2 dBm时达到最大输出功率14.53 dBm.整个芯片传输连接采用共面波导结构,芯片面积为1.06 mm×0.75 mm.     

基于FPGA的超高速时间交织ADC后台校准技术

针对时间交织模数转换器（TI-ADC）三项主要失配误差（采样时间间隔失配误差、偏移失配误差和增益失配误差）,提出一种基于FPGA的数字后台校准技术.失配误差值可通过校准算法得出,此校准算法基于统计近似的数学方法.反馈调节被用来减少TI-ADC的三项主要失配误差.此技术采用片外校准方式,校准算法在FPGA内部完成,校准调节电路在TI-ADC内部完成.实验结果表明：TI-ADC校准后与校准前比较,平均有效位数（ENOB）和平均无杂散动态范围（SFDR）分别提高0.58和11.28dBc,验证了该后台校准技术的有效性.     

Ka-band IQ vector modulator employing GaAs HBTs

The importance of high-performance,low-cost and millimeter-wave transmitters for digital communications and radar applications is increasing.The design and performance of a Ka-band balanced in-phase and quadrature-phase(I-Q)type vector modulator,using GaAs heterojunction bipolar transistors(HBTs)as switching elements,are presented.The balanced technique is used to remove the parasitics of the HBTs to result in near perfect constellations.Measurements of the monolithic microwave integrated circuit(MMIC)chip with a size of 1.89×2.26 mm~2 demonstrate an amplitude error below 1.5 dB and the phase error within 3°between 26 and 40 GHz except for a singular point at 35.6 GHz.The results show that the technique is suitable for millimeter-wave digital communications.     

A 4 GS/s 4 bit ADC with 3.8 GHz analog bandwidth in GaAs HBT technology

An ultra-wideband 4 GS/s 4 bit analog-to-digital converter(ADC)which is fabricated in 2-level interconnect, 1.4μm InGaP/GaAs HBT technology is presented.The ADC has a-3 dB analog bandwidth of 3.8 GHz and an effective resolution bandwidth(ERBW)of 2.6 GHz.The ADC adopts folding-interpolating architecture to minimize its size and complexity.A novel bit synchronization circuit is used in the coarse quantizer to eliminate the glitch codes of the ADC.The measurement results show that the chip achieves larger than 3.4 ENOBs with an input frequency band of DC-2.6 GHz and larger than 3.0 ENOBs within DC-4GHz at 4 GS/s.It has 3.49 ENOBs when increasing input power by 4 dB at 6.001 GHz of input.That indicates that the ADC has the ability of sampling signals from 1st to 3rd Nyquist zones(DC-6 GHz).The measured DNL and INL are both less than±0.15 LSB. The ADC consumes power of 1.98 W and occupies a total area of 1.45×1.45 mm~2.