一个单通道10位160兆每秒的逐次逼近式模数转换器

This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register （SAR） analog-to-digital converter （ADC） in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied.     

基于节点模式势能的光伏并网电力系统机电振荡网络薄弱区域识别

针对光伏（PV）并网后电力系统低频振荡问题,从网络能量角度提出含光伏的电力系统小干扰分析方法,基于节点模式势能法,利用两机系统和四机两区系统进行仿真,重点分析了惯量分布及电抗距离对节点抗扰能力的影响,进而通过各个节点的抗扰能力进行能量分级来识别划分系统的薄弱区域并验证。仿真结果表明,利用节点模式势能法可以清晰地从网络角度体现各个节点的振荡特性及抗扰能力,验证了能量分级进行薄弱区域划分方法的可行性和正确性。