具有8p秒群延时的3~5千兆赫CMOS超宽带功率放大器

本文提出了一种采用线性相位滤波器模型、用于BPSK调制的3~5GHz超宽带系统的差分功率放大器。本文中功率放大器已经采用中芯国际0.18微米CMOS工艺流片验证。为了达到足够的线性度和效率,本功放工作在AB区域,在-0.5dBm的输入1dB压缩点时,输出8.5dBm功率。功耗为28.8mW, 在3~5GHz工作范围内,增益为9.11±0.39dB,群延时在 8ps之内。     

一个采用0.18μm CMOS工艺的3－5GHz超宽带平坦增益低噪声放大器

本论文设计并实现了一个用于UWB脉冲体制的3-5GHz超宽带平坦增益的全差分低噪声放大器。在电路设计上,采用了一种增益平坦化技术,并且利用了串连建峰与并联建峰技术,分别实现了宽带的输入匹配与整个电路大的增益带宽积。同时,利用反馈技术,进一步拓展带宽和削减带内增益波动。此LNA才用SMIC 0.18um CMOS射频工艺流片验证。测试结果表面电路3dB带宽为2.4~5.5GHz,最高增益可达13.2dB,在3－5GHz的带内增益波动仅为＋/- 0.45dB,最低噪声系数为3.2dB．输入匹配性能良好,在2.9~5.4GHz范围内S11<-13dB,电路的输入P1dB为－11.7dBm@5GHz,电路采样1.8v供电,整个差分电路消耗电流9.6mA.     

一种1.8伏带有foldback过流过热保护的低压线性稳压器设计

This paper introduces the design of a l.8 V low dropout voltage regulator （LDO） and a foldback current limit circuit which limits the output current to 3 mA when load over-current occurs. The LDO was implemented in a 0.18 μm CMOS technology. The measured result reveals that the LDO s power supply rejection （PSR） is about -58dB and -54dB at 20Hz and 1kHz respectively,the response time is 4μs and the quiescent currentis 20μA. The designed LDO regulator can work with a supply voltage down to 2.0 V with a drop-out voltage of 200 mV at a maximum load current of 240 mA.     

单芯片极窄微弱脉冲检测系统设计

采用0.18μm CMOS工艺设计了一款单芯片集成极窄微弱脉冲检测系统,该芯片包括输入匹配、放大器、脉冲展宽器、驱动及带隙基准电压电流产生电路。为提高检测系统灵敏度,文章采用了多级放大器级联以及有源电感。测试表明该芯片可以检测1ns脉宽10mV的脉冲,输出数字信号,可以应用于OOK系统接收机,接收超过40M数据率的清晰视频。该芯片低功耗、低成本,具有研究和实践推广价值。     

A 0.18 μm CMOS 3-5 GHz broadband flat gain low noise amplifier

A 3-5 GHz broadband flat gain differential low noise amplifier(LNA) is designed for the impulse radio ultra-wideband(IR-UWB) system.The gain-flatten technique is adopted in this UWB LNA.Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product(GBW).Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations.The prototype is fabricated in the SMIC 0.18μm RF CMOS process.Measurement results show a 3-dB gain band...     

A 3-5 GHz CMOS UWB power amplifier with±8 ps group delay ripple

A differential power amplifier(PA),designed using the linear-phase filter model,for a BPSK modulated ultra-wideband(UWB) system operating in the 3-5 GHz frequency range is presented.The proposed PA was fabricated using 0.18μm SMIC CMOS technology.To achieve sufficient linearity and efficiency,this PA operates in the class-AB region,delivering an output power of 8.5 dBm at an input-1 dB compression point of -0.5 dBm.It consumes 28.8 mW, realizing a flat gain of 9.11±0.39 dB and a very low group delay ripp...