A physical-based pMOSFETs threshold voltage model including the STI stress effect

The physical threshold voltage model of pMOSFETs under shallow trench isolation(STI) stress has been developed.The model is verified by 130 nm technology layout dependent measurement data.The comparison between pMOSFET and nMOSFET model simulations due to STI stress was conducted to show that STI stress induced less threshold voltage shift and more mobility shift for the pMOSFET.The circuit simulations of a nine stage ring oscillator with and without STI stress proved about 11%improvement of average delay time.This indicates the importance of STI stress consideration in circuit design.     

STI应力效应下的pMOSFET阈值电压物理模型

本文提出了浅沟道隔离（STI）应力效应下的P型MOSFET的阈值电压物理模型,并用不同STI版图位置的130纳米的器件数据进行了验证。基于此STI阈值电压模型,我们对比了p型MOSFET和n型MOSFET在STI应力下的阈值电压和迁移率的变化。数据表明,相比n型MOSFET,p型MOSFET的阈值电压更少地受到STI应力影响,但迁移率却更多地受到STI应力影响。基于此STI阈值电压模型,我们进行了九级震荡环电路的模拟。模拟数据显示,适当的STI应力能使电路平均延迟时间提高约11%,同时也说明了STI应力模型在电路设计中的重要性。