排序方式: 共有3条查询结果,搜索用时 0 毫秒
1
1.
2.
本文对后栅工艺高k/金属栅结构NMOSFET偏压温度不稳定性特性进行了研究。在加速应力电压和高温条件下,NMOSFET的阈值电压的退化与时间呈幂指数关系。然而幂指数随应力电压的增大而减小;在本文中,应力从0.6V到12V,幂指数则相应的由0.26减小到0.16。通过对应力前后器件的亚阈值特性分析,在应力过程中没有界面态产生。根据实验数据提取到数值为0.1eV的热激活能,表明偏压温度不稳定性是由栅介质中预先存在的陷阱俘获从衬底隧穿的电子造成的。恢复阶段的测试显示阈值电压的退化与对数时间呈线性关系,同时可以用确定的数学表达式来表明其与应力电压和温度之间的关系。 相似文献
3.
The characteristics of TDDB (time-dependent dielectric breakdown) and SILC (stress-induced leakage current) for an ultra-thin SiO2/HfO2 gate dielectric stack are studied. The EOT (equivalent-oxide-thickness) of the gate stack (Si/SiO2/HfOz/TiN/TiA1/TiN/W) is 0.91 am. The field acceleration factor extracted in TDDB experi- ments is 1.59 s.cm/MV, and the maximum voltage is 1.06 V when the devices operate at 125 ℃ for ten years. A detailed study on the defect generation mechanism induced by SILC is presented to deeply understand the break- down behavior. The trap energy levels can be calculated by the SILC peaks: one S1LC peak is most likely to be caused by the neutral oxygen vacancy in the HfO2 bulk layer at 0.51 eV below the Si conduction band minimum; another SILC peak is induced by the interface traps, which are aligned with the silicon conduction band edge. Fur- thermore, the great difference between the two SILC peaks demonstrates that the degeneration of the high-k layer dominates the breakdown behavior of the extremely thin gate dielectric. 相似文献
1