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This paper presents a capacitor-free CMOS low dropout voltage regulator which has high PSR perfor- mance and low chip area. Pole splitting and gm boosting techniques are employed to achieve good stability. The capacitor-free chip LDO was fabricated in commercial 0.18μm CMOS technology provided by GSMC (Shanghai, China). Measured results show that the capacitor-free LDO has a stable output voltage 1.79 V, when supply voltage changes from 2.5 to 5 V, and the LDO is capable of driving maximum 100 mA load current. The LDO has high power supply rejection about -79 dB at low frequency and -40 dB at 1 MHz frequency, while sacrifice of the LDO's active chip-area is only smaller than 0.02 mm2. 相似文献
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讨论了几种VLSI版图中电容的计算方法;计算集成电路电容的方法有公式法和数值法两大类。利用数值法计算电容的方法包含有限差分法、有限元法、边界元法和格林法等,分析了以上各种方法的计算原理和优缺点。 相似文献
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