排序方式: 共有31条查询结果,搜索用时 15 毫秒
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A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μm CMOS process for W-CDMA application is presented.The transformer not only accomplishes output impedance matching,but also acts as a balun for converting differential signals to single-ended ones.Under a supply voltage of 3.3 V,the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%.The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB,respectively. The die size is 0.91×1.12 mm~2. 相似文献
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本文提出了一种新型的基于轮换触发的除二电路及其基于大信号分析的优化方法。通过减小跟随相输出节点的RC常数,增大锁存相输出节点的RC常数,减小内部信号摆幅和补偿锁存相输出节点漏电流的损失等电路技术,大大拓宽了其工作频带。本论文在SMIC 0.13μm RF CMOS工艺条件下设计了一款原型电路,其后仿工作频率可以达到320MHz到29.6GHz。此外,这款除二电路还应用于两款整数分频锁相环芯片中,分别对频率为4224MHz和10GHz的信号进行分频。测试结果表明,这款除二电路可以对其进行正确分频,而且整体锁相环的带内相噪分别为-94dBC/Hz@10kHz和-84dBc/Hz@10kHz. 相似文献
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根据Bore提出的一种MEMS薄膜断裂强度静电测试结构,给出了一种改进的数学模型,根据此数学模型可以很简单地测出MEMS薄膜的断裂强度.对各种不同尺寸的结构用Coventor软件对所给模型进行了验证,结果表明所得出的数学模型比原文中所给出的数学模型更为准确. 相似文献
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This paper presents a 10-GHz low spur and low jitter phase-locked loop(PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs(1 kHz to 10 MHz);the phase noise is-89 ... 相似文献
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A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consumption at low gain mode. The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm2. It achieves 35 dB conversion gain across 4.9-5.1 GHz, a noise figure of 7.2 dB and an IIP3 of -16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode. 相似文献
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A novel toggled flip-flop(TFF) divide-by-two circuit(DTC) and its optimization method based on a large-signal analysis approach are proposed.By reducing the output RC constant in tracking mode and making it large in latching mode,compressing the internal signal swing as well as compensating the current leaked in the latching mode, the operating frequency range is greatly expanded.Implemented in a SMIC 0.13μm RF CMOS process with a 1.2 V power supply,it can work under an ultra-wide frequency band ranging ... 相似文献
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A fully integrated VCO and divider implemented in SMIC 0.13-μm RFCMOS 1P8M technology with a 1.2 V supply voltage is presented.The frequency of the VCO is tuning from 8.64 to 11.62 GHz while the quadrature LO signals for 802.11a WLAN in 5.8 GHz band or for 802.11b/g WLAN and Bluetooth in 2.4 GHz band can be obtained by a frequency division by 2 or 4,respectively.A 6 bit switched capacitor array is applied for precise tuning of all necessary frequency bands.The testing results show that the VCO has a phas... 相似文献
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