Design of Pipelined ADC Using Op Amp Sharing Technique

This paper presents a 10-bit 20 MS/s pipelined Analog-to-Digital Converter(ADC)using op amp sharing approach and removing Sample and Hold Amplifier(SHA)or SHA-less technique to reach the goal of low-power consumption.This design was fabricated in TSMC 0.18 μm 1P6M CMOS technology.Measurement results show at supply voltage of 1.8 V,a SFDR of 42.46 dB,a SNDR of 39.45 dB,an ENOB of 6.26,and a THD of 41.82 dB are at 1 MHz sinusoidal signal input.In addition,the DNL and INL are 1.4 LSB and 3.23 LSB respectively.The power consumption is 28.8 mW.The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.     

台湾CATV网络光纤到家的迷思

一 前言 台湾CATV的发展在1990年代曾历经欣欣向荣的风光，短短几年的时间，快速地发展到750MHz HFC网络系统，到了2000年进入光纤发展的新世纪，台湾CATV网络的发展似乎停滞不前，仍然以原先建置的750MHz HFC网络为基础提供视讯服务。此时的邻国日本，在CATV网络方面的发展有许多值得借镜之处，日本不仅在大规模的CATV中已逐步采用了大容量、高速和较多频道的FTTH技术．而且，最近又开始在小规模CATV设施中应用FTTH技术。