一款具有新颖的采样保持电路应用于脉冲式超宽带技术的欠采样型模数转换器

本文提出了一款基于CMOS 0.13um,具有新颖的采样保持电路,应用于脉冲式超宽带接收机的欠采样型模数转换器.本文主要的难点在于实现拥有远远高于奈奎斯特频率的输入信号的欠采样型模数转换器。根据我们的了解,本文是当今第二次提出当采样时钟大约在1.056GHz,输入信号超过4GHz的欠采样型模数转换器。电路设计中,我们提出了一款新颖的采样保持电路,解决了信号幅度的衰减和高频输入信号线性度的问题。一款使用零静态功耗动态失调校准比较器被进一步优化,实现了失调,速度以及功耗的要求。测试结果显示,当采样频率为1.056GHz,输入信号高达4.2GHz时,SFDR 为30.1dB。不包括缓冲器,ADC的功耗为30mW,芯片面积为0.6mm2.ADC的FoM是3.75pJ.     

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier for an IR-UWB receiver

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier(THA) in 0.13μm CMOS for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm~2.The ADC achieves a figure of merit of 3.75 pJ/conversion-step.