一种积累型槽栅超势垒二极管

提出了一种积累型槽栅超势垒二极管,该二极管采用N型积累型MOSFET,通过MOSFET的体效应作用降低二极管势垒。当外加很小的正向电压时,在N+区下方以及栅氧化层和N-区界面处形成电子积累的薄层,形成电子电流,进一步降低二极管正向压降;随着外加电压增大,P+区、N-外延区和N+衬底构成的PIN二极管开启,提供大电流。反向阻断时,MOSFET截止,PN结快速耗尽,利用反偏PN结来承担反向耐压。N型积累型MOSFET沟道长度由N+区和N外延区间的N-区长度决定。仿真结果表明,在相同外延层厚度和浓度下,该结构器件的开启电压约为0.23 V,远低于普通PIN二极管的开启电压,较肖特基二极管的开启电压降低约30%,泄漏电流比肖特基二极管小近50倍。     

A novel SOI high-voltage SJ-pLDMOS based on self-adaptive charge balance

A new SOl self-balance （SB） super-junction （S J） pLDMOS with a self-adaptive charge （SAC） layer and its physical model are presented. The SB is an effective way to realize charges balance （CB）. The substrate-assisted depletion （SAD） effect of the lateral SJ is eliminated by the self-adaptive inversion electrons provided by the SAC. At the same time, high concentration dynamic self-adaptive electrons effectively enhance the electric field （EI） of the dielectric buried layer and increase breakdown voltage （BV）. E1 = 600 V/μm and BV =- 237 V are obtained by 3D simulation on a 0.375-μm-thick dielectric layer and a 2.5-μm-thick top silicon layer. The optimized structure realizes the specific on resistance （Ron,sp） of 0.01319Ω·cm2, FOM （FOM = BV2/R p） of 4.26 MW/cm2 under a 11 μm length （Ld） drift region.     

具有部分界面等电势浮空埋层的高压SOI PLDMOS

A novel silicon-on-insulator（SOI） high-voltage pLDMOS is presented with a partial interface equipotential floating buried layer（FBL） and its analytical model is analyzed in this paper.The surface heavily doped p-top layers,interface floating buried N⁺/P⁺ layers,and three-step field plates are designed carefully in the FBL SOI pLDMOS to optimize the electric field distribution of the drift region and reduce the specific resistance.On the condition of ESIMOX（epoxy separated by implanted oxygen）,it has been shown that the breakdown voltage of the FBL SOI pLDMOS is increased from—232 V of the conventional SOI to—425 V and the specific resistance R_on,sp is reduced from 0.88 to 0.2424Ω·cm².