一种用于短距离器件的433/868 MHz的带I/Q校准的低中频接收机

A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier （PA）, frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR （image rejection ratio） so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of-60 dBm and a control gain of 60 dB. The S11 reaches -20 dB at 433 MHz and -10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm^2 including the bias circuit.     

用于带有片上时钟的窄带低中频接收机的自适应数字校准技术

Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented.The calibration and control system,which is adopted to ensure an achievable signal-to-noise ratio and bit error rate,consists of a digitally controlled,high resolution dB-linear automatic gain control（AGC）,an inphase（I） and quadrature（Q） gain and phase mismatch calibration,and an automatic frequency calibration（AFC） of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer.The calibration system has a low design complexity with little power and small die area.Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB,respectively,which means the image rejection ratio is better than 60 dB.In addition,the calibration time of the AFC is 1.12 μs only with a reference clock of 100 MHz.     

用于434/868MHz FSK/OOK CMOS发射机的锁相环设计

一种可输出434/868MHz信号的Σ-Δ分数分频锁相环在0.35μmCMOS工艺中集成。该发射机系统采用直接调制锁相环分频比的方式实现FSK调制,OOK的调制则通过功率预放大器的开-关实现。为了降低芯片的成本和功耗,发射机采用了电流数字可控的压控振荡器(VCO),以及片上双端-单端转换电路,并对分频器的功耗设计进行研究。经测试表明,锁相环在868MHz载波频偏为10kHz、100kHz和3MHz处的相位噪声分别为-75dBc/Hz、-104dBc/Hz和-131dBc/Hz,其中的VCO在100kHz频偏处的相位噪声为-108dBc/Hz。在发送模式时,100kHz相邻信道上的功率与载波功率之比小于-50dB。在直流电压2.5V的工作条件下,锁相环的电流为12.5mA,包括功率预放大器和锁相环在内的发送机总面积为2mm2。