一种高精度时钟同步电路

本文提出了一种基于交错延迟单元和动态补偿电路的高精度时钟同步电路结构,HPSC,并 可用在对时钟要求较高的大规模分布网络中。此电路采用了基于SMD的粗调结构和动态补偿 电路的细调结构,可在两个时钟周期内完成粗调并在接下来三个时钟周期内完成细调,其误 差小于3.8 ps。本电路使用SMIC 0.13 μm 1P6M 工艺设计并实现,供电电压1.2 V。其输入 频率为200MHz-800MHz,占空比为20%-80%,有效面积 245μm×134μm,功耗为1.64 mW@500MHz     

一种基于双三极管并联的UWB 窄脉冲发生器

脉冲产生器是IR-UWB通信系统的重要组成模块之一。提出了一种高可靠性的窄脉冲发生电路。该脉冲产生电路基于并联的双射频三极管所产生的雪崩效应与LC电路阻尼原理,产生一阶微分高斯脉冲波形。双三级管的并联设计加速了雪崩效应,降低了工作电压,易于电路实现。当其中单只三极管损坏时,电路仍然可以依靠另一只进行工作。实验测试结果表明：该电路所产生的脉冲峰峰值约为12.88V,脉冲宽度约为1.6ns,可以用于IR-UWB通信系统。     

A novel dual-feed low-dropout regulator

A novel dual-feed (DF) low-dropout (LDO) is presented. The DF-LDO adopts dual control loops to maintain the output voltage. The dual control loops include a feedback loop and a feedforward loop. There is an equilibrium point in dual control loops, and the equilibrium point is the output voltage of the DF-LDO. In addition, the transient performance is optimized by adjusting the damping ratio and natural frequency. With a 1 μF decoupling capacitor, the proposed DF-LDO is fabricated in a 0.18 μm CMOS process and its output voltage is 1.5 V. When the workload changes from 100 μA to 100 mA in 100 ns, load regulation of 7 mV for a 100 mA step is achieved, the settling time is 997 ns and the undershoot is 12.8 mV; when the workload changes from 100 mA to 100 μA in 100 ns, the settling time is 249 ns with an imperceptible overshoot.