SOI-LIGBT寄生晶体管电流增益的研究

采用二维器件模拟仿真软件Tsuprem4和Medici模拟了SOI-LIGBT的n型缓冲层掺杂剂量、阳极p+阱区长度、漂移区长度以及阳极所加电压对SOI-LIGBT寄生晶体管电流增益β的影响,通过理论分析定性的解释了产生上述现象的原因和机理,并且通过实验测试结果进一步验证了分析结论的正确性。其中,n型缓冲层掺杂剂量对电流增益β的影响最为明显,漂移区长度的影响最弱。基本完成了对SOI-LIGBT寄生晶体管电流增益β主要工艺影响因素的定性分析,对于SOI-LIGBT的设计有一定的借鉴意义。     

Process optimization of a deep trench isolation structure for high voltage SOI devices

In this work, the process reasons for weak point formation of the deep trench on SOI wafer have been analyzed in detail. The optimized trench process is also proposed. It is found that there are two main reasons: one is over-etching laterally of silicon on the surface of buried oxide caused by fringe effect; the other is slowly growth rate of isolation oxide in the concave silicon corner of trench bottom. In order to improve the isolation performance of deep trench, two feasible ways for optimizing trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon corner at weak point, increasing the applied voltage by 15-20V at the same leakage current. The proposed new trench isolation process has been verified in foundry’s 0.5-μm HV SOI technology.     

Process optimization of a deep trench isolation structure for high voltage SOI devices

The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail.An optimized trench process is also proposed.It is found that there are two main reasons:one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect;and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom.In order to improve the isolation performance of the deep trench,two feasible ways for optimizi...     

Double RESURF nLDMOS功率器件的优化设计

基于漂移区表面具有单个P-top层Double RESURF nLDMOS的结构和耐压机理,提出了具有P-top层终端结构的Double RESURF nLDMOS结构,并通过利用SENTAURUS TSUPREM4和DEVICES软件进行优化设计。P-top层终端结构不仅降低了击穿电压对P-top层参数的敏感度,而且在漂移区引入一个附加的电场峰值,使漂移区电场分布进一步趋于平坦化。与传统Single RESURF和普通Double RESURF器件相对比,击穿电压可以分别提高约13.5%和4%,导通电阻却提高了11.8%和6%,但在满足击穿电压相等的条件下,该结构通过控制P-top层的位置和漂移区剂量可以使导通电阻降低约37%。     

nLEDMOS热载流子效应在版图及工艺上的改善方法

Two layout and process key parameters for improving high voltage nLEDMOS （n-type lateral extended drain MOS） transistor hot carrier performance have been identified. Increasing the space between Hv-pwell and n-drift region and reducing the n-drift implant dose can dramatically reduce the device hot carder degradations, for the maximum impact ionization rate near the Bird Beak decreases or its location moves away from the Si/SiO2 interface. This conclusion has been analyzed in detail by using the MEDICI simulator and it is also confirmed by the test results.     

200V高压SOI PLDMOS研究

提出了一种200V高压SOI PLDMOS器件结构,重点研究了SOI LDMOS的击穿电压、导通电阻等电参数与漂移区注入剂量、漏端缓冲层、Nbody注入剂量及场极板长度等之间的关系。经过专业半导体仿真软件TSUPREM-4和MEDICI模拟仿真,在0.8μm埋氧层、10μmSOI层材料上设计得到了关态耐压248V、开态饱和电流2.5×10-4A/μm、导通电阻2.1（105Ω＊μm的SOI PLDMOS,该器件可以满足PDP扫描驱动芯片等的应用需求。     

高压gg-LDMOS在ESD应力条件下的热特性研究

The thermal characteristics of high voltage gg-LDMOS under ESD stress conditions are investigated in detail based on the Sentaurus process and device simulators.The total heat and lattice temperature distributions along the Si–SiO2 interface under different stress conditions are presented and the physical mechanisms are discussed in detail.The influence of structure parameters on peak lattice temperature is also discussed,which is useful for designers to optimize the parameters of LDMSO for better ESD performance.     

700V高压LDMOS器件瞬态失效机理研究

详细分析了700V横向双扩散金属氧化物半导体(LDMOS)器件瞬态失效机理的特性。研究表明触发器件寄生晶体管开启的失效功率不仅与器件内部温度有关,同时也与电场分布有关。器件温度影响寄生阱电阻和衬底电流的大小,而电场分布影响器件内部碰撞电离。器件温度与电场分布均与栅脉冲参数有密切关系。为了阐述栅脉冲参数对器件温度的影响,模拟仿真了器件的热响应曲线。     

600V CoolMOS优化设计

CoolMOS具有优越的直流特性。为了设计出一个600V CoolMOS结构,首先CoolMOS的结构入手,结合电荷平衡理论,分析了其高击穿电压BV、低导通电阻Ron的原理。通过理论计算,得到相关的设计参数,并结合TCAD软件对Cool-MOS的多个参数（外延参数、注入剂量、单胞尺寸、推阱时间）进行了优化。最终得到击穿电压为630 V,特征导通电阻RonA仅为12.5 mΩ.cm-2的CoolMOS结构,器件特性大大优于传统功率MOSFET。     

SOI-LDMOS器件改善电安全工作区后驼峰现象的研究

研究了高压SOI-LDMOS器件在引入P-sink结构改善电安全工作区(E-SOA)后I-V特性曲线呈现的驼峰现象(hump)。首先将驼峰现象出现后器件的源端总电流分成电子电流与空穴电流单独分析,确定高栅压下电子电流阶梯上升是驼峰现象产生的表面原因,进而通过仿真分析出Kirk效应导致的空穴电流在表面漂移区中电导调制是驼峰现象产生的根本原因。最后,根据对驼峰现象的分析,设计出新器件结构成功消除了驼峰现象,为今后不同类型LDMOS器件改善I-V曲线驼峰现象提供了理论指导。