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A 35-130 MHz/300-360 MHz phase-locked loop frequency synthesizer for △-∑ analog-to-digital con- verter (ADC) in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode (300-360 MHz) or in low-power mode (35-130 MHz) to satisfy the ADC's requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the fre- quency synthesizer achieves a phase-noise of-132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of-112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply. 相似文献
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基于0.25 μm GaAs赝高电子迁移晶体管(pHEMT)工艺,研制了一种1.0~2.4 GHz的放大衰减多功能芯片,该芯片具有低噪声、高线性度和增益可数控调节等特点。电路由第一级低噪声放大器、4位数控衰减器、第二级低噪声放大器依次级联构成,同时在片上集成了TTL驱动电路。为获得较大的增益和良好的线性度,两级低噪声放大器均采用共源共栅结构(Cascode)。测试结果表明,在1.0~2.4 GHz频带范围内,该芯片基态小信号增益约为36 dB,噪声系数小于1.8 dB,输出1 dB压缩点功率大于16 dBm,增益调节范围为15 dB,调节步进1 dB,衰减RMS误差小于0.3 dB,输入输出电压驻波比小于1.5。其中放大器采用单电源+5 V供电,静态电流小于110 mA,TTL驱动电路采用-5 V供电,静态功耗小于3 mA。整个芯片的尺寸为3.5 mm×1.5 mm×0.1 mm。 相似文献
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本文提出了一个适用于Δ-Σ模数转换器的基于锁相环结构的频率综合器,该频率综合器使用65纳米CMOS工艺实现,频率范围为35-130和300-360兆赫兹。文中提出的频率综合器能够工作在低相位噪声模式和低功耗模式,从而满足系统要求。为了实现这两个模式的切换,片上集成了一个连接4分频器的高频LC压控振荡器和一个连接2分频器的环形压控振荡器。测试结果表明,在1.2伏电源电压下,该频率综合器在低相位噪声模式下消耗1.74毫瓦功耗,1兆频偏处的相位噪声为-132dBc/Hz,标准差周期抖动为1.12皮秒;在低功耗模式下消耗0.92毫瓦功耗,1兆频偏处的相位噪声为-112dBc/Hz,标准差周期抖动为7.23皮秒。 相似文献
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