Measurement matrix design for CS-MIMO radar using multi-objective optimization

In this paper, we design a measurement matrix for a compressive sensing-multiple-input multiple-output radar in the presence of clutter and interference. To optimize the measurement matrix, three main criteria are considered simultaneously to improve detection and sparse recovery performance while suppressing clutter and interference. To this end, we consider three well-known criteria including Bhattacharyya distance, mutual coherency of sensing matrix, and signal-to-clutter-plus-interference ratio. Due to the use of simultaneous multi-objective functions, a multi-objective optimization (MOO) framework is exploited. Some numerical examples are provided to illustrate the achieved improvement of our proposed method in target detection and sparse recovery performance. Simulation results show that the proposed MOO technique for measurement matrix design can achieve superior performance in target detection compared with Gaussian random measurement matrix technique.     

Modeling and Analyzing of Millimeter Wave Heterogeneous Cellular Networks by Poisson Hole Process

Wireless Personal Communications - In this paper, a novel Poisson hole process (PHP) modeling of wireless networks is proposed. Contrary to the prior PHP models with circular-shaped holes, we...     

A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications

A 12-GS/s 8-bit digital-to-analog converter (DAC) enables 24 Gb/s signaling over conventional backplane channels. Designed in a 90-nm CMOS process, the circuit occupies an area of 670 mum times 350 mum and achieves INL and DNL of 0.31 and 0.28LSB, respectively. Measured SNDR and SFDR are 41 dB and 51 dB at 750 MHz and 32.5 dB and 35 dB at 1.5 GHz. Measured SDR and 3-dB bandwidth using 12 GS/s random data are 32 dB and 7.1 GHz, respectively. The power dissipation is 190 mW from 1-V and 1.8-V power supplies.     

Survivor memory reduction in the Viterbi algorithm

This paper presents a novel approach for implementation of the Viterbi algorithm, wherein survivor paths are generally kept in as low as one half of the storage required for traditional trace-back methods. Survivor memory reduction is obtained by storing only the useful part of the survivor paths. In other words, the redundancy in the survivor paths is removed. A decoder using this approach not only requires significantly less memory, but also runs faster than conventional decoders. Some instances of this approach are explicitly presented.     

Design and VLSI implementation for a WCDMA multipath searcher

The third generation (3G) of cellular communications standards is based on wideband CDMA. The wideband signal experiences frequency selective fading due to multipath propagation. To mitigate this effect, a RAKE receiver is typically used to coherently combine the signal energy received on different multipaths. An effective multipath searcher is, therefore, required to identify the delayed versions of the transmitted signal with low probability of false alarm and misdetection. This paper presents an efficient and novel WCDMA multipath searcher design and VLSI architecture that provides a good compromise between complexity, performance, and power consumption. Novel multipath searcher algorithms such as time domain interleaving and peak detection are also presented. The proposed searcher was implemented in 0.18 /spl mu/m CMOS technology and requires only 150 k gates for a total area of 1.5 mm/sup 2/ consuming 6.6 mw at 100 MHz. The functionality and performance of the searcher was verified under realistic conditions using a channel emulator.     

Accumulate-Repeat-Accumulate Codes

In this paper, we propose an innovative channel coding scheme called accumulate-repeat-accumulate (ARA) codes. This class of codes can be viewed as serial turbo-like codes or as a subclass of low-density parity check (LDPC) codes, and they have a projected graph or protograph representation; this allows for high-speed iterative decoding implementation using belief propagation. An ARA code can be viewed as precoded repeat accumulate (RA) code with puncturing or as precoded irregular repeat accumulate (IRA) code, where simply an accumulator is chosen as the precoder. The amount of performance improvement due to the precoder will be called precoding gain. Using density evolution on their associated protographs, we find some rate-1/2 ARA codes, with a maximum variable node degree of 5 for which a minimum bit SNR as low as 0.08 dB from channel capacity threshold is achieved as the block size goes to infinity. Such a low threshold cannot be achieved by RA, IRA, or unstructured irregular LDPC codes with the same constraint on the maximum variable node degree. Furthermore, by puncturing the inner accumulator, we can construct families of higher rate ARA codes with thresholds that stay close to their respective channel capacity thresholds uniformly. Iterative decoding simulation results are provided and compared with turbo codes. In addition to iterative decoding analysis, we analyzed the performance of ARA codes with maximum-likelihood (ML) decoding. By obtaining the weight distribution of these codes and through existing tightest bounds we have shown that the ML SNR threshold of ARA codes also approaches very closely to that of random codes. These codes have better interleaving gain than turbo codes