Compact Harmonic Filter Design and Fabrication Using IPD Technology

An integrated passive device (IPD) technology has been developed to meet the ever increasing needs of size and cost reduction in radio front-end transceiver module applications. Electromagnetic (EM) simulation was used extensively in the design of the process technology and the optimization of inductor and harmonic filter designs and layouts. Parameters such as inductor shape, inner diameter, metal thickness, metal width, and substrate thickness have been optimized to provide inductors with high quality factors. The technology includes 1) a thick plated gold metal process to reduce resistive loss; 2) MIM capacitors using PECVD SiN dielectric layer; 3) airbridges for inductor underpass and capacitor pick-up; and 4) a 10 mil finished GaAs substrate to improve inductor quality factor. Both lumped element circuit simulations and electromagnetic (EM) simulations have been used in the harmonic filter circuit designs for high accuracy and fast design cycle time. This paper will present the EM simulation calibration and demonstrate the importance of using EM simulation in the filter design in order to achieve first-time success in wafer fabrication. The fabricated IPD devices have insertion loss of 0.5 dB and harmonic rejections of 30dB with die size of 1.42 mm for high band (1710 MHz-1910 MHz) and 1.89 mm for low band (824-915 MHz) harmonic filters.     

High-performance self-aligned (Al,Ga)As/(In,Ga)As pseudomorphicHIGFETs

Transconductance as high as 676 mS/mm at 300 K was observed to 0.7×10-μm² n-channel devices (HIGFETs) made on epilayers with Al_0.3Ga_0.7As insulator thickness of 200 Å and In_0.15Ga_0.85As channel thickness of 150 Å. An FET K value (K=W_g Uε/2aL_g) as large as 10.6 mA/V ² was also measured from another device with transconductance of 411 mS/mm. The high K values are achieved under normal FET operation without hole-injection or drain-avalanche breakdown effects. These results demonstrate the promise of pseudomorphic (Al,Ga)As/(In,Ga)As HIGFETs for high-performance circuit applications     

Overview of complementary GaAs technology for high-speed VLSIcircuits

A self-aligned complementary GaAs (CGaAs) technology (developed at Motorola) for low-power, portable, digital and mixed-mode circuits is being extended to address high-speed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature, it is years ahead of CMOS in terms of fast gate delays at low power supply voltages. Complementary circuits operating at 0.9 V have demonstrated power-delay products of 0.01 μW/MHz/gate. Propagation delays of unipolar circuits are as low as 25 ps. Logic families can be mixed on a chip to trade power for delay. CGaAs is being evaluated for VLSI applications through the design of a PowerPC-architecture microprocessor     

Static random-access memory based on self-aligned-gate (Al,Ga)As/n+-GaAs superlattice modulation-doped FETs

A 64 bit, fully decoded static random-access memory (SRAM) has been fabricated utilising self-aligned-gate (Al,Ga)As/n+-GaAs superlattice modulation-doped FETs (MODFETs) for the first time. Read access times of 1.1 ns at 270 ?W/bit and minimum write-enable pulse widths less than 2 ns were demonstrated at room temperature. Typical room-temperature extrinsic transconductances and output conductances of 240 mS/mm and 7 mS/mm, respectively, were observed for the superlattice MODFET devices.     

Submicron p-channel (Al,Ga)As/(In,Ga)As HIGFETs

Submicron p-channel (Al,Ga)As/(In,Ga)As HIGFETs have been optimized for application to high-performance complementary GaAs circuits. Major issues with submicron and deep submicron (L_g⩽0.5-μm) P-channel HIGFETs have been the severe short-channel effects, such as high subthreshold leakage currents and high output conductances. With optimization of the p-type self-aligned implant schedule, control of impurity contamination at the substrate/buffer interfaces and increase of the resistivity of the unintentionally-doped GaAs buffers, high-performance submicron devices have been realized. Typically, 0.5-μm P-HIGFETs yielded room temperature transconductances of 90 mS/mm, drain currents at V_gs =V_ds=-1.5 V of 63 mA/mm, and subthreshold leakage currents near 1 nA. Subthreshold slope of 90 mV/decade and output conductances under 5 mS/mm were realized     

0.9-V DSP blocks: a 15-ns 4-k SRAM and a 45-ns 16-bmultiply/accumulator

4-k SRAM and 16-b multiply/accumulate DSP blocks have been designed and fabricated in complementary heterostructure GaAs. Both circuits operate from 1.5 V to below 0.9 V. The SRAM uses 28,272 transistors in an area of 2.44 mm². Cell size is 278 μm ² at 1.0-μm gate length. Measured results show an access delay of 5.3 ns at 1.5 V and 15.0 ns at 0.9 V. At 0.9 V, the power dissipated is 0.36 mW. The CGaAs multiplier uses a 16-b modified Booth architecture with a 3-way 40-b accumulator. The multiplier uses 11,200 transistors in an area of 1.23 mm². Measured delay is 19.0 ns at 1.5 V and 44.7 ns at 0.9 V. At 0.9 V, current is less than 0.4 mA     

Enhancement-Mode GaAs n-Channel MOSFET

This letter introduces the first enhancement-mode GaAs n-channel MOSFETs with a high channel mobility and an unpinned Fermi level at the oxide/GaAs interface. The NMOSFETs feature an In_0.3Ga_0.7 As channel layer, a channel mobility of up to 6207 cm²/Vmiddots, and a dielectric stack thickness of 13.1-18.7 nm. Enhancement-mode NMOSFETs with a gate length of 1 mum, a source/drain spacing of 3 mum, and a threshold voltage of 0.05 V show a saturation current, transconductance, on-resistance, and subthreshold swing of 243 mA/mm, 81 mS/mm, 8.0 Omegamiddotmm, and 162 mV/dec, respectively     

Experimental observation of velocity overshoot in n-channelAlGaAs/InGaAs/GaAs enhancement mode MODFETs

Velocity overshoot phenomena in n-channel Al-GaAs/InGaAs/GaAs enhancement mode MODFETs have been investigated for gate lengths ranging from 1 to 0.5 μm. The study is based on Motorola's established CGaAs ^TM technology. The observed average electron velocity υ _aυ under the gate is 1.05, 1.34, 1.48, and 1.71×10 ⁷ cm/s for a gate length L_G of 1, 0.7, 0.6, and 0.5 μm, respectively. The presence of velocity overshoot in InGaAs channels is clearly proven with average electron velocities exceeding the steady-state saturation velocity of ≅1×10⁷ cm/s for L_G⩽0.7 μm, and with the significant increase of υ_aυ with shorter gate length     

High purity and chrome-doped GaAs buffer layers grown by liquid phase epitaxy for mesfet application

High purity GaAs buffer layers of carrier concentration in the low (l-5)×l0^l4/cm³ range with 77K electron mobility over 100,000 cm²/V-sec and 300K mobility around 8000 cm?/ V-sec have been grown by liquid phase epitaxy on Cr-doped GaAs substrates using the graphite sliding boat method. The high purity has been achieved with systematic and concurrent long term bake-outs (24 hrs) of both LPE melt and substrate, both exposed to the H₂ ambient gas stream at 775?C, prior to epitaxial growth at 700?C. Substrate surface degradation was reduced by using Ga:GaAs etch melts that were undersaturated at 700?C by 5? to 40?C. Best buffer layer morphologies with regard to surface planarity were obtained using etch melts that were saturated by near 85% of weight of GaAs at 700°C. The importance of substrate preconditioning in order to achieve the low ( 1 -2)×l0¹⁴ was examined and found to be critical. Melt and substrate bake outs at 800?C, and use of a 40?C undersaturated etch melt prior to epitaxial growth at 800?C resulted in a p-type layer of carrier concentration, 1 .9×l0^l2/cm³ and resistivity 1×10⁵ ohm-cm. Chromium doping at 700?C resulted in buffer layers with sheet resistivities greater than 10 ohms/sq and low pinhole densities.     

Residual donors and acceptors in high-purity GaAs and InP grown by hydride VPE

Residual donors and acceptors in epitaxial films of GaAs and InP grown by the hydride vapor phase epitaxy technique were investigated using the complementary techniques of photothermal ionization spectroscopy and variabletemperature photoluminescence. High-purity samples of GaAs grown in three different laboratories were compared and high-purity InP samples were also measured. The dominant shallow acceptors in the GaAs samples were found to be C and Zn, and deep Cu and Mn acceptors were also observed. The donors Si, S, and Ge were observed in the GaAs with S being dominant. A clear correlation was observed between the gas phase stoichiometry during growth and the relative incorporation of column IV donors (Si and Ge) and column VI donors (S) in GaAs. Substrate quality, source purity, and atmospheric contamination of the growth system were found to influence the photoluminescence spectra of the GaAs samples. In the InP samples three shallow acceptors were observed including Zn, an unknown shallow acceptor level with E_A ≃ 21 meV, and an acceptor which may be either C or Mg. An unusual deep, structured emission band was also seen. The donors in the hydride InP were also found to be present in LPE InP and are believed to be Si and S.