Sub-threshold R-MOSFET tunable resistor technique

An R-MOSFET resistor structure that enables extension of the MOSFETs' operation into sub-threshold region while preserving good linearity performance is presented. The technique essentially relies upon a linear current division between two nonlinear branches each comprising a linear resistor and a MOSFET operating at sub-threshold inversion. The feasibility of the sub-threshold R-MOSFET structure is demonstrated via breadboard experiment using array transistors, and via simulation using a 0.18 mum CMOS process     

Current-feedback source-degenerated CMOS transconductor with very high linearity

A highly linear current-feedback (CF) transconductor with resistive source-degeneration is developed in CMOS technology. It consists of a differential source follower cascaded with a classical source-degenerated transconductor with its drain current fed back to modulate the bias of the source follower for nonlinearity cancellation, yielding an overall linear transfer function in the circuit. Designed using a 0.35 /spl mu/m CMOS process for a continuous-time delta-sigma application, the CF transconductor achieves a total harmonic distortion better than -80 dB up to 1 MHz for a 0.8 V input differential voltage while the supply voltage is 2.5 V and the power consumption is 3.4 mW.     

Branch-and-Bound-Based Local Search Heuristics for Train Timetabling on Single-Track Railway Network

The modified formulation and two branch-and-bound-based local search heuristic algorithms for train timetabling in single-track railway network in the planning application are proposed. The original local search heuristic is modified such that when a neighbor of a currently tested resolved conflict for improvement is evaluated, the depth-first search branch-and-bound algorithm is employed with two branching rules: least-lower-bound and least-delay-time. The detailed implementation of the proposed heuristic algorithms are described, including the neighborhood definitions of overtaking and crossing conflicts, the procedure to detect overtaking and crossing conflicts, and a recursive procedure for the depth-first search branch-and-bound algorithm. The proposed heuristic algorithms, the original heuristic, the equivalent manual solution method and the exact solution method are compared using a toy problem and four problems (26-train, 50-train, 76-train and 108-train) in the Thailand Southern line railway network, which consisted of 266 single-track segments, 15 double-track segments, 282 stations/sidings, and total distance of 1577 km. The proposed heuristic algorithm with the least-lower-bound branching rule outperforms the other heuristics in terms of the solution quality with up to 2.827 % improvement over the equivalent manual solution method and less than 8 % optimality gap. The proposed heuristic algorithms require longer time to terminate than the original heuristic. The proposed heuristic algorithm with the least-lower-bound branching rule converges faster than that with the least-delay-time branching rule in all test problems. Based on the empirical results, the proposed heuristic algorithms are solvable in polynomial time. Furthermore, the proposed heuristic algorithm with the least-lower-bound branching rule is enhanced by embedding a uniform sampling strategy, and it is found that the total CPU time can be saved by about 50 % with marginally worse solution quality.     

Performance Analysis and Design of Triple-Resonance Interstage Peaking for Wide-Band Cascaded CMOS Amplifiers

The analysis and design of the two promising candidates for interstage bandwidth enhancement of integrated wide-band cascaded amplifiers (CAs), namely series-shunt (SH) and shunt-series (HS) triple-resonance peaking, are presented. The principal operation of both peaking networks is described qualitatively in time-domain where the inherent bandwidth superiority of SH peaking is revealed. With the help of triple resonance concept, a rigorous and insightful analysis is then given in frequency domain. Analytical equations applicable to both networks have been derived to enable the proper inductance selection and to quantify the bandwidth advantage of SH peaking. In addition, various frequency characteristics of the networks are discussed through the investigation of their triple resonant frequency locations. This is followed by detailed analysis on the important nonidealities due to transistors gate resistance and inductors' losses. The effectiveness of theoretical analysis is demonstrated via design and simulation of SHCA and HSCA with identical number of stages, gain and power consumption. The results show good agreement between theoretical analysis and simulation where the SHCA outperforms its HS counterpart in bandwidth while other performances are practically identical.     

Enhanced switched-current comparator

Practical techniques for accuracy and speed enhancement in switched-current (SI) comparators are presented. Both techniques require minimum added complexity and, more importantly, possess no performance penalty for the comparator in terms of noise and power. Extensive simulations indicate an enhanced SI comparator with an improvement in resolution of >2.5 bit/s and a speed increase of a factor of 1.35 over those of the basic SI comparator. This makes it feasible for the implementation of an SI comparator with >8.5 bit resolution at an operating speed of >270 MHz for a power consumption of <1.7 mW     

High frequency current mode oscillator employing fTintegration technique

A low distortion high frequency oscillator is described, which is a development of the recently proposed f_T-integrator, in which an amplitude control circuit is embedded inside the integrator. Simulation results suggest that, for the oscillation range 1-2.6 GHz, the total harmonic distortion (THD) of the output current signal is well below 0.5% for the output current level at 50% modulation depth (peak-to-peak). The phase noise of the oscillator is simulated to be -72 dBc/Hz at 1 MHz offset for 1% THD output current     

High-speed switched-current matched filter for WCDMA receivers

A matched filter (MF) based upon the cascoded class AB SI technique is presented for spread-spectrum communication receivers. Accomplished through both architectural and circuit developments, the filter's features include low power, high speed and compatibility with standard CMOS process inherent to SI signal processing. For performance assessment, a 31-tap 80 MS/s SI MF for despreading task in future high-speed WCDMA receivers is demonstrated.     

Architecture for low-voltage switched-current complex bandpassfilters

An architecture for the switched-current (SI) realisation of complex filters is presented, based upon the signal flow-graph method. Also briefly discussed is a practical design flow for SI complex filters, based on that for traditional real SI filter designs. A verification of the architecture is given via the design and simulation of a fifth-order complex SI bandpass filter with 1 MHz centre frequency and bandwidth, implemented using a low-voltage class AB neutralised SI scheme     

Low-voltage class AB switched-current technique

A low-voltage class AB technique for high-speed and medium-resolution switched-current (SI) signal processing is described. The technique essentially uses the basic class AB SI memory with error-neutralisation and dummy switch schemes to reduce output conductance and charge-injection errors. Simulated results of the balanced class AB memory and bilinear integrator operating at 100 MHz sampling frequency and 1.6 V supply indicates that precision better than 8 bits is entirely feasible over the extreme process and temperature corners     

Linear current-mode lossy integrator for integrated current-modewave-active filters

A linear current-mode lossy integrator well suited for the implementation of emerging current-mode wave-active filters is proposed. It can operate at high frequencies with low power supply requirements. Simulation results of a linear phase wave active filter realised using a circuit with a supply voltage of 2.5 V are included