A high-density NAND EEPROM with block-page programming formicrocomputer applications

A high-density, 5-V-only, 4-Mb CMOS EEPROM with a NAND-structured cell using Fowler-Nordheim tunneling for programming is discussed. The block-page mode is utilized for high-speed programming and easy microprocessor interface. On-chip test circuits for shortening test time and for evaluating cell characteristics yield highly reliable EEPROMs. The NAND EEPROM has many applications for microcomputer systems that require small size and large nonvolatile storage systems with low power consumption     

A side-wall transfer-transistor cell (SWATT cell) for highlyreliable multi-level NAND EEPROMs

A multi-level NAND Flash memory cell, using a new Side-WAll Transfer-Transistor (SWATT) structure, has been developed for a high performance and low bit cost Flash EEPROM. With the SWATT cell, a relatively wide threshold voltage (V_th) distribution of about 1.1 V is sufficient for a 4-level memory cell in contrast to a narrow 0.6 V distribution that is required for a conventional 4-level NAND cell. The key technology that allows this wide V_th distribution is the Transfer Transistor which is located at the side wall of the Shallow Trench Isolation (STI) region and is connected in parallel with the floating gate transistor. During read, the Transfer Transistors of the unselected cells (connected in series with the selected cell) function as pass transistors. So, even if the V_th of the unselected floating gate transistor is higher than the control gate voltage, the unselected cell will be in the ON state. As a result, the V_th distribution of the floating gate transistor can be wider and the programming can be faster because the number of program/verify cycles can be reduced. Furthermore, the SWATT cell results in a very small cell size of 0.57 μm² for a 0.35 μm rule. Thus, the SWATT cell combines a small cell size with a multi-level scheme to realize a very low bit cost. This paper describes the process technology and the device performance of the SWATT cell, which can be used to realize NAND EEPROM's of 512 Mbit and beyond     

Polymers of α-substituted benzyl methacrylates as a new type of electron-beam resist

Summary Polymer of α-substituted benzyl methacrylate was found to be used as a new type of positive electron-beam resist, which forms methacrylic acid units in the polymer chain on the exposure to electron-beam and can be developed using alkaline solution as a developer. The sensitivity was dependent on the bulkiness of the ester group and the number of ?-hydrogen atoms in the ester group. The sensitivity and γ-value of atactic poly(α, α-dimethylbenzyl methacrylate) were improved by a factor of more than three over poly (methyl methacrylate).     

Reliability issues of flash memory cells

Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) flash memory and the NAND structure EEPROM are discussed. Disturbs during programming, write/erase endurance, charge loss of both devices are reviewed, and the reliability of the tunnel oxide and the interpoly dielectric are described. It is shown that bipolarity F-N programming/erase, which is used in the NAND EEPROM, improves the charge to breakdown and decreases the stress-induced leakage current     

An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell

A 5-V-only high-density (512 K*8 bit) electrically erasable and programmable read-only memory (EEPROM) has been designed and fabricated by using a NAND-structured cell with 1.0- mu m design rules. The average cell area per bit is 12.9 mu m/sup 2/. Block erasing, successive programming, and random reading are achieved using a newly developed NAND-cell control circuit. Typical erasing time is 1.0 ms and page-programming time is 4.0 ms, equivalent to 1.0 mu s/bit. A dynamic sensing system is introduced to sense the small cell current. Typical read access time is 1.6 mu s. The die size is 10.7*15.3 mm/sup 2/.<>     

BiCMOS circuit technology for high-speed DRAMs

A BiCMOS circuit technology featured by a novel bit-line sense amplifier has been developed. The bit-line sense amplifier is composed of a BiCMOS differential amplifier, the impedance-converting means featured by the CMOS current mirror circuit or the clocked CMOS inverter between the bit line and the base node of the BiCMOS differential amplifier, and a conventional CMOS flip-flop. This technology can reduce the access time to half that of a conventional CMOS DRAM access time. Applied to a 1-kb DRAM test chip, a new BiCMOS circuit technology was successfully verified. Furthermore, the sensitivity and area penalty of the new BiCMOS bit-line sense amplifier and future applications to megabit DRAMs are discussed     

A 130-mm2, 256-Mbit NAND flash with shallow trenchisolation technology

A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 μm is achieved with 0.25-μm STI. The memory cell is shrunk to 0.29 μm², which realizes a 130-mm² , 256-Mbit flash memory. Peripheral transistors are scaled with memory cells in order to reduce fabrication process steps. A voltage down converter, which generates 2.5-V constant internal power source, is applied to protect the scaled transistors. An improved bit-line clamp sensing scheme achieves 3.8-μs first access time in spite of long and tight pitch bit-line. A 1-kbyte page mode with 35-ns serial data out realizes 25-Mbyte/s read throughput. An incremental step pulse with a bit by bit verify scheme programs 1-k cells in 1-V Vt distribution within 200 μs. That realizes 4.4-Mbyte/s programming throughput     

Time duration of output pulse in electron-beam-pumped CdS laser

Time duration of the output pulse of electron-beam-pumped CdS laser was investigated. It increased with increase of the excitation current density and was of the order of 100 ns at the beam voltage of 25 kV. It was shown experimentally that the quenching of the laser oscillation is due to the rise of the threshold current density as the result of the temperature rise in the active region of the crystal. The expression for the duration of laser oscillation based on this model was derived and compared with the experimental results. The dependence of the duration on the excitation current density was explained by this model.     

Fabrication of an optical directional coupler of CdTe by electron beam lithography and ion etching

Various kinds of high resolution techniques such as ion etching, chemical etching, ion implantation, and electron beam lithography are studied for fabricating CdTe optical integrated circuits. It is found that the ion-etching rate of CdTe is high and has only a small dependence on crystal orientation. A special chemical etching solution for aluminum on CdTe that does not corrode CdTe and proton implanted CdTe is used for high resolution patterning of CdTe. The smooth patterns in PMMA resist produced by an electron beam exposure is replicated deep into 2.5 μm of CdTe face through the aluminum layer. Rib guides and a rib-type optical directional coupler are fabricated from planar guides by using proton implantation which makes refractive index change on CdTe face. The two-dimensional optical confinement is observed. A coupling coefficient ofk simeq 0.39mm^-1is observed in the rib-type optical directional coupler.