Monte Carlo Simulations of High-Performance Implant Free In0.3Ga 0.7As Nano-MOSFETs for Low-Power CMOS Applications

The potential performance of implant free heterostructure In_0.3Ga_0.7As channel MOSFETs with gate lengths of 30, 20, and 15 nm is investigated using state-of-the-art Monte Carlo (MC) device simulations. The simulations are carefully calibrated against the electron mobility and sheet density measured on fabricated III-V MOSFET structures with a high-kappa dielectric. The MC simulations show that the 30 nm gate length implant free MOSFET can deliver a drive current of 2174 muA/mum at 0.7 V supply voltage. The drive current increases to 2542 muA/mum in the 20 nm gate length device, saturating at 2535 muA/mum in the 15 nm gate length one. When quantum confinement corrections are included into MC simulations, they have a negligible effect on the drive current in the 30 and 20 nm gate length transistors but lower the 15 nm gate length device drive current at 0.7 V supply voltage by 10%. When compared to equivalent Si based MOSFETs, the implant free heterostructure MOSFETs can deliver a very high performance at low supply voltage, making them suitable for low-power high-performance CMOS applications     

Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator

Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-κ gate dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon and in the high-κ dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains in the high-κ gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow. At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the 25 nm gate length MOSFET.     

Quantum Aspects of Resolving Discrete Charges in ‘Atomistic’ Device Simulations

In ‘atomistic’ device simulation the resolving of discrete charges onto a fine grained simulation mesh can lead to problems. The sharply resolved coulomb potential can cause simulation artefacts to appear in classical simulation environments using Boltzmann or Fermi-Dirac statistics. Various methods have been proposed in an effort to reduce or eliminate artefacts such as the trapping of mobile carriers in sharply resolved Coulomb wells, however they have met with limited success. In this paper we show an alternative approach for handling discrete charges in drift diffusion ‘atomistic’ simulations by properly introducing the related quantum mechanical effects using the Density Gradient formalism. This produces the desired effect of eliminating the trapping of mobile charge in heavily doped regions of the device.     

3D Parallel Simulations of Fluctuation Effects in pHEMTs

The use of 3D simulations is essential in order to study the effects of fluctuations when devices are scaled to deep submicron dimensions. A 3D drift-diffusion device simulator has been developed to effectively simulate pseudomorphic high electron mobility transistors (pHEMTs) on a distributed memory multiprocessor computer. The drift-diffusion equations are discretized using a finite element method on an unstructured tetrahedral mesh. The obtained set of equations is solved in parallel on an arbitrary number of processors using the message-passing interface library. We have applied our simulator to a 120 nm pHEMT based on the Al_0.3Ga_0.7As/In_0.2Ga_0.8As interface and carried out a calibration to real experimental data.     

The Use of Quantum Potentials for Confinement and Tunnelling in Semiconductor Devices

As MOSFETs are scaled to sub 100 nm dimensions, quantum mechanical confinement in the direction normal to the silicon dioxide interface and tunnelling (through the gate oxide, band-to-band and from source-to-drain) start to strongly affect their characteristics. Recently it has been demonstrated that first order quantum corrections can be successfully introduced in self-consistent drift diffusion-type models using Quantum Potentials. In this paper we describe the introduction of such quantum corrections within a full 3D drift diffusion simulation framework. We compare the two most popular quantum potential techniques: density gradient and the effective potential approaches, in terms of their justification, accuracy and computational efficiency. The usefulness of their 3D implementation is demonstrated with examples of statistical simulations of intrinsic fluctuation effects in decanano MOSFETs introduced by discrete random dopants. We also discuss the capability of the density gradient formalism to handle direct source-to-drain tunnelling in sub 10 nm double-gate MOSFETS, illustrated in comparison with Non-Equilibrium Green's Functions simulations.     

Numerical study of the effect of the doping profile on the threshold voltage of narrow-channel MOS transistor

A two-dimensional MOS process and device simulator, called IMPEDANCE, is used to study the influence of various doping profiles of stopper and channel implantations on the threshold voltage of narrow-channel MOS transistor (made with LOCOS isolation technology). For enhancement-mode transistors without channel implantation the lateral spread of the stopper implantation is the main factor for the threshold voltage increase with decreasing channel width. However the increase of the channel implantation dose reduces the dependence of the threshold voltage on the width especially at higher ion energies. In case of depletion-mode transistors the dependence of the threshold voltage on width is stronger owing to: (1) the existence of a lateral p-n junction between the channel and the stopper region and (2) the weaker gate control of the channel carriers.     

Capacitance fluctuations in bulk MOSFETs due to random discrete dopants

Accuracy of timing in circuits and systems using nanoscale transistors is crucial and is dependent, to first order, on the capacitances of the load transistors. It is accepted that variation in parameters will be intrinsic to such devices due to, among other factors, the discrete nature of the doping. It is likely that one such parameter exhibiting variation will be capacitance. Here we investigate, using 3-dimensional simulation, the fluctuation in gate and drain capacitance in a 30 nm MOSFET due to random discrete doping.     

Simulation study of the 20 nm gate-length Ge implant-free quantum well p-MOSFET

In this paper a drift diffusion simulation study of a 20 nm gate-length implant-free quantum well germanium p-MOSFET is presented, which covers the impact of mobility, velocity saturation and density of interface states on the transistor performance. The parasitic gate capacitance was also studied. The simulations show that the 20 nm gate-length implant-free quantum-well transistor design has good electrostatic integrity and performance potential.     

Simulation of hole-mobility in doped relaxed and strained Ge

As silicon CMOS begins to reach the limits of its performance, alternative channel materials are being considered. Thus there is renewed interest in employing Germanium for p-MOSFETs, due to the significant improvement in hole mobility as compared to silicon for undoped materials. Of considerable interest from a device point of view is the transport in doped layers. We investigate hole transport at high carrier-densities in doped Germanium layers using a bulk 6-band k·p Monte Carlo simulator, and show that both dynamic and multi-ion screening play a significant role in describing the resulting transport.     

Complete Monte Carlo RF analysis of “real”short-channel compound FET's

A comprehensive RF analysis technique based on ensemble Monte Carlo (EMC) simulation of compound FET's with realistic device geometry is presented. Y-parameters are obtained through Fourier transformation of the EMC transients in response to small changes in the terminal voltages. The terminal currents are statistically enhanced and filtered to allow for reliable y-parameters extraction. Improved analytic procedure for extracting the intrinsic device small-signal circuit components is described. As a result, stable y-parameters and reliable circuit components can he extracted for the whole range of device operation voltages. Parasitic components like contact and gate resistances are included in the y-parameters at a post processing stage to facilitate the forecast of the performance figures of merit of real devices. The developed RF technique has been applied in the EMC simulation of pseudomorphic HEMT's (pHEMT's) fabricated at the Glasgow Nanoelectronics Research Center. Good agreement has been achieved between the simulated and measured small-signal circuit components and performance figures of merit