Multilayer and multiproduct masks: cost reduction methodology

The cost of reticles is growing twice as fast as the overall cost ofnew process development for technologies beyond the 100-nm node , . In order for the integrated circuit design to continuouslybenefit from the shrinkpath in alignment with Moore's law , the industry should explore cost-effectiveapproaches for the mask data [(intellectual property (IP)] placement alternativeto the standard methodology of one mask for one layer of one product . The implementation of multi-IPplacements, using multilayer or multiproduct (shuttle) masks, is based oncomplex technical and economical analysis to maximize mask return on investment(ROI) over the product lifetime. The key criteria include the ability to matchlayers or products on one plate with respect to the CD control and patterndensity and the expected time or fab volume prior to the conversion to thededicated mask set for successful products. This work analyzes the links betweenthe IP content of the mask, the product market price, and the wafer volume.As an example, by taking into account the cost of the exposure and of themask, one can show that for 100-nm technology, positive ROI would be achievedfor a product or test vehicle with volume depending on the architecture ofthe multilayer mask set. We compare the key challenges of the two basic multi-IPmask approaches, the multilayer and the multiproduct masks, and discuss thebest conditions for their implementation. Directions for future research arealso proposed.     

Observation of two types of trapping centers in thin filmtransistors using charge pumping technique

Using voltage- and frequency-dependent charge pumping techniques, we observed two types of trapping centers with different densities, cross-sections, and trapped charges at the polysilicon-(TEOS) gate oxide interface in thin film transistors (TFT's). These observations can be explained in terms of nonuniform energetic or spatial distribution of the traps due to the channel polysilicon grain structure or related to the process-induced interface defects. Mechanisms are discussed     

Enhanced electron trapping near channel edges in NMOS transistors

Charge trapping in the gate oxide of NMOS transistors due to constant-voltage Fowler-Nordheim injection was investigated. Results from several different measurement methods consistently indicated strongly enhanced electron trapping in the gate oxide near the channel edges and in the gate oxide overlaps above drain and source, although net positive charge was observed in the bulk of the channel. The edge trapping effect could increase the electrical channel length by as much as 0.5 μm and is independent of the channel length. Possible reasons for the observed phenomena are discussed     

Effects of combined x-ray Irradiation and hot-electron injection on NMOS transistors

Changes of NMOS transistor parameters after combined stress of x-ray irradiation and hot-electron injection were studied. We found that, in general, the resultant effects depended strongly on the order of the stress sequence. Of the parameters studied, oxide charge trapping depends more significantly on the stress sequence than the generation of interface traps. Interface trap transformation process and nonuniform defect distribution along the channel have been observed under certain stress conditions. Consequences of the above effects on the transistor dc parameters are discussed.     

Hot-carrier effects on gate-induced-drain-leakage (GIDL) current inthin-film SOI/NMOSFET's

The gate-induced-drain-leakage (GIDL) currents in thin-film SOI/NMOSFET's have been studied before and after front-channel hot-carrier stress. Both the normal-mode stress (with the front gate biased beyond the threshold voltage and the drain biased at a high positive voltage, while the source is grounded with the back gate) and the reverse-mode stress (with the source and drain interchanged) have been investigated. The following significant changes have been observed: i) an increase of the off-state drain GIDL current after the normal-mode stress, especially in the low gate field region, and ii) a decrease of the off-state GIDL current after the reverse-mode stress, especially in the high gate field region. These changes can be attributed to the hot-carrier induced interface traps and their effects on the parasitic bipolar transistor gain in the thin-film SOI/NMOSFET     

Effects of X-ray irradiation on GIDL in MOSFETs

The effect of X-ray irradiation on the gate-induced drain leakage (GIDL) is shown to be mostly due to the electrostatic effect of the trapped positive charge in n-channel MOSFETs. In p-channel MOSFETs, in addition, irradiation increases the interface-state-assisted tunneling component of the GIDL. In both n- and p-channel MOSFETs, a forming gas anneal at 400°C completely removes all effects of irradiation on the GIDL     

Hot-carrier effects on interface-trap capture cross sections inMOSFETs as studied by charge pumping

A rapid charge-pumping method was used to measure the interface-trap parameters in MOSFETs. The geometric mean of the electron and hole interface-trap capture cross sections decreases significantly (as much as two orders of magnitude) after Fowler-Nordheim (F-N) injection, and gradually recovers toward its original value. This effect is consistent with the interface-trap transformation process observed in MOS capacitors