On the use of multi-path inductorless TIAs for larger transimpedance limit

This paper discusses the use of mutli-path inductorless transimpedance amplifiers (TIAs), consisting of several different second-order shunt-feedback sub-TIAs (SF-sTIAs) driven by the photodiode, to break the single-stage technology-dependent transimpedance limit. The advantage of the MP-TIA that is explored in this work is in its third-order transfer function, which provides additional degrees of freedom in tailoring the performance. Pole and zero locations of the MP-TIA transfer function are examined and verified with behavioural simulations. The theoretical transimpedance limit for MP-TIAs based on two SF-sTIAs is derived. The possibility of further increasing the transimpedance limit vs bandwidth trade-off by combining three and four sub-TIAs is investigated with simulations. A transistor-level design example of an MP-TIA is presented. The 0.13-μm CMOS MP-TIA achieves the largest figure-of-merit among published TIAs.     

A technique for microwave ranging and remote phase synchronization

A very precise electrical-distance measurement system that is also capable of supplying a phase-synchronous signal to a remote location is required for a new type of radio telescope, the large adaptive reflector (LAR). The system is based on a round-trip phase synchronization method, and is designed to work over a free-space path of length up to 1 km, the focal distance of the telescope. The electrical length of this path is to be measured with an accuracy of 70 μm and a phase-stable signal is to be provided at the remote end as the basis for a local-oscillator signal of stability equivalent to 5° at 22 GHz. Phase synchronization and distance measurement are accomplished with the same microwave ranging circuit. The distance measurement is derived from phase comparison of high-frequency signals, including a novel use of the Chinese Remainder Theorem (CRT) to resolve the unavoidable wavelength ambiguity. The design of the system is described, and limitations imposed by phase-measurement and frequency-setting accuracy are explored. Errors due to atmospheric dispersion are negligible under most circumstances. Accurate phase synchronization has been demonstrated over a free-space path of ~300 m. The complete system has been simulated under noisy conditions, and its ability to meet the specifications demonstrated     

Two-port noise figure optimization of source-degenerated cascode CMOS LNAs

This paper presents a noise figure optimization technique for source-degenerated cascode CMOS LNAs with lossy gate inductors. The optimization technique, based on two-port theory, takes into account second order parasitic components. The effect of inductive source degeneration on LNA noise parameters is discussed. Measured noise figures agree well with the simulations confirming the accuracy of the noise model and allowing us to investigate the contributions of various components to the overall noise figure. A 0.18-μm CMOS LNA with an integrated inductor (Q = 7.5) achieves a noise figure of 1.16 dB and a return loss of 20 dB at 1.4 GHz, drawing 39 mA from a 1.8-V voltage supply, having gain (S ₂₁) of 14.5 dB, input P1dB of ?17.5 dBm, and input IP3 of ?13 dBm. LNAs with external inductors having quality factor of Q = 170 and Q = 40 achieve noise figures of 0.65 dB and 0.68 dB and a return loss of 20 dB at 1.4 GHz, drawing 37 mA from a 1.8-V voltage supply, having gain (S ₂₁) of 17 dB, input P1dB of ?22 dBm, and input IP3 of ?14 dBm. The large power consumption of the presented designs was intentionally selected in order to reduce the noise figure, an acceptable trade-off for LNA’s targeted for radio telescope applications, and to assess the impact of the large currents flowing through interconnect metals on the noise figure     

Wide‐band aperture array using a four‐channel manifold‐type planar multiplexer and digital 2‐D IIR filterbank

Emerging wide‐band communications and spectrum‐sensing systems demand support for multiple electronically scanned beams while maintaining a frequency independent, constant far‐field beam width. Realizing existing phased‐array technology on a digital scale is computationally intensive. Moreover, digitizing wide‐band signals at Nyquist rate requires complex high‐speed analog‐to‐digital converters (ADCs), which is challenging for real developments driven by the current ADC technology. A low‐complexity alternative proposed in this paper is the use of radio‐frequency (RF) channelizers for spectrum division followed by sub‐sampling of the RF sub‐bands, which results in extensive reduction of the necessary ADC operative frequency. The RF‐channelized array signals are directionally filtered using 2‐D digital filterbanks. This mixed‐domain RF/digital aperture array allows sub‐sampling, without utilizing multi‐rate 2‐D systolic arrays, which are difficult to realize in practice. Simulated examples showing 14–19 dB of rejection of wide‐band interference and noise for a processed bandwidth of 1.6 GHz are demonstrated. The sampling rate is 400 MHz. The proposed VLSI hardware uses a single‐phase clock signal of 400 MHz. Prototype hardware realizations and measurement using 65‐nm Xilinx field‐programmable gate arrays, as well as Cadence RTL synthesis results including gate counts, area‐time complexity, and dynamic power consumption for a 45‐nm CMOS circuit operating at B _DC = 1.1 V, are presented. Copyright © 2016 John Wiley & Sons, Ltd.     

A four-quadrant current multiplier/divider cell with four transistors

We propose a four quadrant six transistor current multiplier cell based on the translinear principle. The cell is further modified by using resistive feedback to remove two PNP transistors hence reducing the total transistor count to four NPN transistors only. This not only eliminates the problem of mismatch between the two transistor types but allows the cell to operate both as a current multiplier/divider depending on the resistive feedback ratio. The modified cell can also multiply mixed current/voltage signals and operates equally well with NMOS transistors instead of bipolar ones. Experimental results using discrete transistors confirming the correct operation of the cell are provided.     

Parametric CMOS upconverters and downconverters

This paper discusses parametric CMOS mixers as potential radio‐frequency front‐end contributors to advanced mm‐wave and sub‐mm‐wave wireless communicators. It outlines fundamental concepts underlying parametric circuit operation highlighting its benefits with regards to power consumption, speed, and noise performance. The implementation of parametric CMOS architectures is detailed. Critical device properties and figures of merit are shown. Measurement results of prototype designs are given. Copyright © 2013 John Wiley & Sons, Ltd.     

A Technique for Differential Noise Figure Measurement of Differential LNAs

This paper presents an approach to measure the noise figure of a differential low-noise amplifier (LNA) based on familiar ldquocold-hotrdquo single-ended noise figure measurements. To demonstrate the usefulness of this approach, measurement results are presented for a wideband differential LNA designed to be used as the first stage of the receiver in the Square Kilometre Array radio telescope. The presented LNA achieves less than 0.41 dB of differential noise figure in the 700 MHz to 1.4 GHz band, differential S₁₁ <-13 dB, differential S₂₁ between 18 and 14 dB, single-ended output P1 dB of -8.2 dBm, and output IP3 of -1 dBm while consuming 81 mA from a 1.3-V supply. The approach of measuring the differential noise figure may be automated with one switch at the output of a standard noise source and one switch at the input to a standard noise figure analyzer or a noise figure meter, allowing for automated noise figure measurements of differential LNAs based on the differential pair topology.     

Electronically scanned RF-to-bits beam aperture arrays using 2-D IIR spatially bandpass digital filters

A beamforming system based on two-dimensional (2-D) spatially bandpass infinite impulse response (IIR) plane wave filtering is presented in a multi-dimensional signal processing perspective and the implementation details are discussed. Real-time implementation of such beamforming systems requires modeling of computational electromagnetics for the antennas, radio frequency (RF) analog design aspects for low-noise amplifiers (LNAs), mixed-signal aspects for signal quantization and sampling and finally, digital architectures for the spatially bandpass plane wave filters proposed in Joshi et al. (IEEE Trans Very Large Scale Integr Syst 20(12):2241–2254, 2012). Multi-dimensional spatio-temporal spectral properties of down-converted RF plane wave signals are reviewed and derivation of the spatially bandpass filter transfer function is presented. An example of a wideband antipodal Vivaldi antenna is simulated at 1 GHz. Potential RF receiver chains are identified including a design of a tunable combline microstrip bandpass filter with tuning range 0.8–1.1 GHz. The 1st-order sensitivity analysis of the beam filter 2-D $\mathbf z $ -domain transfer function shows that for a 12-bits of fixed-point precision, the maximum percentage error in the 2-D magnitude frequency response due to quantization is as low as $0.3\,\%$ . Monte-Carlo simulations are used to study the effect of quantization on the bit error rate (BER) performance of the beamforming system. 5-bit analog to digital converter (ADC) precision with 8-bit internal arithmetic precision provides a gain of approximately 16 dB for a BER of $10^{-3}$ with respect to the no beamforming case. ASIC Synthesis results of the beam filter in 45 nm CMOS verifies a real time operating frequency of 429 MHz.     

Sub-0.2 dB Noise Figure Wideband Room-Temperature CMOS LNA With Non-50 Ω Signal-Source Impedance

This paper presents a wideband low-noise amplifier (LNA) designed to be used as the first stage of the receiver in the Square Kilometer Array radio telescope. The LNA design procedure and its layout features are discussed. The noise figure optimization procedure determines the signal-source resistance that results in reduced noise figure. When used in the radio telescope, the required signal-source resistance will be presented by the telescope custom-made antenna elements. The LNA, designed in 90 nm bulk CMOS, achieves sub-0.2 dB noise figure from 800 MHz to 1400 MHz, return loss of more than 11 dB, gain of more than 17 dB driven into a 50 load, output 1 dB compression point of 2 dBm, output IP3 of 12 dBm, and output IP2 of 22 dBm while consuming 43 mA from a 1 V supply. In the LNA implementation presented in this paper the load choke inductor and the source inductor are integrated whereas the gate-, bias-, and the choke-inductor between two transistors of the cascode are external. The noise figure of the presented LNA is to our knowledge the lowest noise figure achieved by a power matched wideband CMOS LNA at room temperature.