A Multistage Closed-loop Sigma-Delta modulator (MSCL)

A new family of high order Sigma Delta modulators called MSCL (Multi Stage Closed-loop) is presented in this paper. They use a global feedback to lower the sensitivity to circuit imperfections. This feedback from the output of the modulator is the sum of the output of each comparator so that no digital prefiltering is required before summing up these signals. However, easy calibration will be required to compensate for the feedback imperfections.MSCL modulators present the same insensitivity to circuit imperfections as classical multi-order one-bit converters, but reach the performance of high-order MASH (MultistAge noise SHaping) modulators. They help make high-order low-pass or band-pass modulators without limit cycles so that their quantizing noise characteristics are similar to those predicted by the linear simplified model.     

A 14-bit 250 kS/s two-step inverter-based incremental $$\varSigma \varDelta$$ ADC for CMOS image sensor in $$0.18\,\upmu \hbox {m}$$0.18μm technology

This paper presents an ultra-low-power, bulk-driven, source-degenerated fully differential transconductor (FD-OTA), operating in subthreshold region. The source-degeneration (SD) and bulk-drive ensure linearity and rail-to-rail input swing. The flipped voltage follower and SD resistor perform V–I conversion in input core with power efficient class AB mode of operation. The reduction in open loop gain and gain bandwidth (GBW) of bulk-drive is compensated by applying partial positive feedback at diode connected MOSFET pair. The current gain from input core to output load side is set (1:1) in OTA₁ and (1:4) in OTA₂. The OTA₂ offers increased transconductance and GBW whereas self-cascode load increases the output impedance and overall gain of the FD-OTAs. Both the input core and common source self-cascode load operate in class AB mode so these FD-OTAs provide enhanced slew rates. These OTAs have been employed to implement Biquadratic low-frequency G_m-C filter suitable for bio-signal applications. The proposed OTA₂ has used dual supply voltage of ± 0.3 V and dissipates around 70 nW power and provides 62 dB FD-open loop gain with GBW of 7.73 kHz while driving the FD-load of 2 × 15 pF. The Cadence VIRTUOSO environment using UMC 0.18 µm CMOS process technology has been used to simulate the proposed circuit. The Simulation results verified fully differential total harmonic distortion of ? 72 dB, for 1.2 V_p–p signal at 200 Hz frequency in unity gain configuration with resistive degeneration of 1 MΩ for OTA₁.     

Operation of an optoelectronic crossbar switch containing a terabit-per-second free-space optical interconnect

The experimental operation of a terabit-per-second scale optoelectronic connection to a silicon very-large-scale-integrated circuit is described. A demonstrator system, in the form of an optoelectronic crossbar switch, has been constructed as a technology test bed. The assembly and testing of the components making up the system, including a flip-chipped InGaAs-GaAs optical interface chip, are reported. Using optical inputs to the electronic switching chip, single-channel routing of data through the system at the design rate of 250 Mb/s (without internal fan-out) was achieved. With 4000 optical inputs, this corresponds to a potential aggregate data input of a terabit per second into the single 14.6 /spl times/ 15.6 mm CMOS chip. In addition 50-Mb/s data rates were switched utilizing the full internal optical fan-out included in the system to complete the required connectivity. This simultaneous input of data across the chip corresponds to an aggregate data input of 0.2 Tb/s. The experimental system also utilized optical distribution of clock signals across the CMOS chip.     

New wideband sigma-delta convertor

A new kind of sigma-delta modulator made with a double integrator and a bandpass stage is presented. It can reduce the oversampling ratio or increase the bandwidth for a constant sampling frequency compared with equivalent complexity modulators.<>     

Design and construction of an optoelectronic crossbar switchcontaining a terabit per second free-space optical interconnect

The completed detailed design and initial phases of construction of an optoelectronic crossbar demonstrator are presented. The experimental system uses hybrid very large scale integrated optoelectronics technology whereby InGaAs-based detectors and modulators are flip-chip bonded onto silicon integrated circuits. The system aims to demonstrate a 1-Tb/s aggregate data input/output to a single chip by means of free-space optics     

A self-calibration scheme for extended frequency-band-decomposition sigma-delta ADC

Frequency-band-decomposition (FBD) is a good candidate to be used to increase the bandwidths of ADC converters based on sigma-delta modulators for software and cognitive radio applications where we need to convert wide bandwidths. Each modulator processes a part of the band of the input signal which is then passed through a digital filter. In the case of large mismatches in the analog modulators, a new solution, called extended frequency-band-decomposition (EFBD) can be used. As an example, this solution can allow for a 4% error in the central frequencies without significant degradation of its performance when the digital processing part is paired with the analog modulators. A calibration of the digital part is thus required to reach these theoretical performances. This paper will focus on a self-calibration algorithm for an EFBD. The algorithm helps minimize the quantization noise of the EFBD and helps to flatten the signal transfer function.     

Extended frequency-band-decomposition sigma–delta A/D converter

Parallelism can be used to increase the bandwidths of ADC converters based on sigma–delta modulators. Each modulator converts a part of the input signal band and is followed by a digital filter. Unfortunately, solutions using bandpass sigma–delta modulators are very sensitive to the position of the modulators’ central frequencies. This paper shows the feasibility of a frequency-band-decomposition (FBD) ADC using continuous time bandpass sigma–delta modulators, even in the case of large analog mismatches. The major benefit of such a solution, called extended-frequency-band-decomposition (EFBD) is its low sensitivity to analog parameters. For example, a relative error in the central frequencies of 4% can be accepted without significant degradation in the performance (other published FBD ADCs require a precision of the central frequencies better than 0.1%). This paper will focus on the performance which can be reached with this system, and the architecture of the digital part. The quantization of coefficients and operators will be addressed. It will be shown that a 14 bit resolution can be theoretically reached using 10 sixth-order bandpass modulators at a sampling frequency of 800 MHz which results in a bandwidth of 80 MHz centered around 200 MHz (the resolution depends on the effective quality factor of the filters of the analog modulators).     

Influence of the feedback DAC delay on continuous-time bandpassΣΔ coverter

An analysis of the effect of the feedback digital-to-analogue converter (DAC) delay on the synthesis results of continuous-time ΣΔ bandpass modulators is presented. It is shown that non-null values of the feedback DAC delay can be optimal with respect to the filter gain margin     

Design and construction of the high-speed optoelectronic memory system demonstrator

The high-speed optoelectronic memory system project is concerned with the reduction of latency within multiprocessor computer systems (a key problem) by the use of optoelectronics and associated packaging technologies. System demonstrators have been constructed to enable the evaluation of the technologies in terms of manufacturability. The system combines fiber, free space, and planar integrated optical waveguide technologies to augment the electronic memory and the processor components. Modeling and simulation techniques were developed toward the analysis and design of board-integrated waveguide transmission characteristics and optical interfacing. We describe the fabrication, assembly, and simulation of the major components within the system.     

Novel loop architectures for enhancing linearity and resolution of analog-to-digital converters

This paper proposes three mixed (analog and digital) loop architectures which involve an analog-to-digital converter and enhance its linearity and its resolution. Their benefits are discussed with mathematical models and high-level simulations (the ADC inserted in the loops is then a passive sigma-delta structure). One of the loop topologies is particularly highlighted: it is ideally able to enhance resolution by 5 bits without damaging bandwidth. The only added analog element is an active differential low-pass filter. The other operators are fully digital: a predictor and some models of the analog parts. The effect of some defaults, such as mismatch and common mode, is illustrated by high-level simulations. The needed accuracy for the digital parameters is evaluated to 16 bits. The test of a prototype realized in a 0.35 μm CMOS technology validates the principle and demonstrates that the critical element of the structure is the active differential filter.