A digital pixel sensor array with programmable dynamic range

This paper presents a digital pixel sensor (DPS) array employing a time domain analogue-to-digital conversion (ADC) technique featuring adaptive dynamic range and programmable pixel response. The digital pixel comprises a photodiode, a voltage comparator, and an 8-bit static memory. The conversion characteristics of the ADC are determined by an array-based digital control circuit, which linearizes the pixel response, and sets the conversion range. The ADC response is adapted to different lighting conditions by setting a single clock frequency. Dynamic range compression was also experimentally demonstrated. This clearly shows the potential of the proposed technique in overcoming the limited dynamic range typically imposed by the number of bits in a DPS. A 64 /spl times/ 64 pixel array prototype was manufactured in a 0.35-/spl mu/m, five-metal, single poly, CMOS process. Measurement results indicate a 100 dB dynamic range, a 41-s mean dark time and an average current of 1.6 /spl mu/A per DPS.     

An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform

In this paper, an efficient architecture for the Finite Ridgelet Transform (FRIT) suitable for VLSI implementation based on a parallel, systolic Finite Radon Transform (FRAT) and a Haar Discrete Wavelet Transform (DWT) sub-block, respectively is presented. The FRAT sub-block is a novel parametrisable, scalable and high performance core with a time complexity of O(p ²), where p is the block size. Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) implementations are carried out to analyse the performance of the FRIT core developed.

Developing pressure sensors from impregnated textile sandwiched in inkjet-printed electrodes

Journal of Materials Science: Materials in Electronics - This work presents an interesting fabrication route toward development of pressure sensing patch by utilizing electrically conductive cotton...     

Arbitrated Time-to-First Spike CMOS Image Sensor With On-Chip Histogram Equalization

This paper presents a time-to-first spike (TFS) and address event representation (AER)-based CMOS vision sensor performing image capture and on-chip histogram equalization (HE). The pixel values are read-out using an asynchronous handshaking type of read-out, while the HE processing is carried out using simple and yet robust digital timer occupying a very small silicon area (0.1times0.6 mm²). Low-power operation (10 nA per pixel) is achieved since the pixels are only allowed to switch once per frame. Once the pixel is acknowledged, it is granted access to the bus and then forced into a stand-by mode until the next frame cycle starts again. Timing errors inherent in AER-type of imagers are reduced using a number of novel techniques such as fair and fast arbitration using toggled priority (TP), higher-radix, and pipelined arbitration. A verilog simulator was developed in order to simulate the effect of timing errors encountered in AER-based imagers. A prototype chip was implemented in AMIS 0.35 mum process with a silicon area of 3.1times3.2 mm². Successful operation of the prototype is illustrated through experimental measurements     

A compact 3D VLSI classifier using bagging threshold network ensembles

A bagging ensemble consists of a set of classifiers trained independently and combined by a majority vote. Such a combination improves generalization performance but can require large amounts of memory and computation, a serious drawback for addressing portable real-time pattern recognition applications. We report here a compact three-dimensional (3D) multiprecision very large-scale integration (VLSI) implementation of a bagging ensemble. In our circuit, individual classifiers are decision trees implemented as threshold networks - one layer of threshold logic units (TLUs) followed by combinatorial logic functions. The hardware was fabricated using 0.7-/spl mu/m CMOS technology and packaged using MCM-V micro-packaging technology. The 3D chip implements up to 192 TLUs operating at a speed of up to 48 GCPPS and implemented in a volume of (/spl omega/ /spl times/ L /spl times/ h) = (2 /spl times/ 2 /spl times/ 0.7) cm/sup 3/. The 3D circuit features a high level of programmability and flexibility offering the possibility to make an efficient use of the hardware resources in order to reduce the power consumption. Successful operation of the 3D chip for various precisions and ensemble sizes is demonstrated through an electronic nose application.     

Bayesian learning using Gaussian process for gas identification

In this paper, a novel gas identification approach based on Gaussian process (GP) combined with principal components analysis is proposed. The effectiveness of this approach has been successfully demonstrated on an experimentally obtained dataset. Our aim is the identification of different gases with an array of commercial Taguchi gas sensors (TGS) as well as microelectronic gas sensors. The proposed approach is shown to outperform both K nearest neighbor (KNN) and multilayer perceptron (MLP) classifiers.     

A novel adaptive logarithmic digital pixel sensor

A major problem associated with complementary metal-oxide-semiconductor and charge couple device imagers is their limited dynamic range (DR), typically 60-70 dB. This falls far short of covering the wide illumination ranges found in natural scenes (typically 120-140 dB). Biological retinas are known to feature adaptive, logarithmic-type responses enabling them to cover a very wide DR, without compromising the resolution. This letter presents a novel way to realize such an adaptive logarithmic response by combining a digital time domain vision sensor and a simple adaptive digital quantizer. This letter presents the theory and experimental results for an adaptive logarithmic response sensor featuring over 100-dB DR.     

PWM digital pixel sensor based on asynchronous self-resetting scheme

In this letter, a pulse-width modulated digital pixel sensor is presented along with its inherent advantages such as low power consumption and wide operating range. The pixel, which comprises an analog processor and an 8-bit memory cell, operates in an asynchronous self-resetting mode. In contrast to most CMOS image sensors, in our approach, the photocurrent signal is encoded as a pulse-width signal, and converted to an 8-bit digital code using a Gray counter. The dynamic range of the pixel can be adapted by simply modulating the clock frequency of the counter. To test the operation of the proposed pixel architecture, an image sensor array has been designed and fabricated in a 0.35-/spl mu/m CMOS technology, where each pixel occupies an area of 45/spl times/45 /spl mu/m/sup 2/. Here, the operation of the sensor is demonstrated through experimental results.     

Design and analysis of energy recyclable bidirectional converter with digital controller for multichannel microstimulators

The power supply modulated microstimulator system can drive an expandable electrode array with reduced heat generation across the current drivers and high stimulation efficiency. Here, we present a comprehensive analytical modelling of the system to investigate internal and external energy flow during biphasic stimulation pulses spanning over varying loading configurations (e.g. number of electrodes, and stimulation current amplitude) that were not covered by existing works on the power supply modulated microstimulators. This paper fills the research gap by presenting the systematic tools for attaining insights of a stimulator system featuring a bidirectional DC–DC converter with an algorithmic digital controller. The models employed here are based on traditional analytical methods such as transfer functions and state-space dynamic models incorporating various circuit elements incurring power loss. With the models, the behaviour and power efficiency under a wide range of parameters associated with stimulator are attained. Numerical assessment reveals that the digital controller can track the output supply voltage at the phase transition boundaries just in tens of switching cycles. The system was also studied on a verification platform, where the internal signals of the digital controller were carefully examined. Measurement results show that the system behavior well matched to the simulation results, demonstrating the effectiveness of the analytical system model for obtaining key insights for generic large-scale micro-stimulator designs.     

Adaptive-Quantization Digital Image Sensor for Low-Power Image Compression

The recent emergence of new applications in the area of wireless video sensor network and ultra-low-power biomedical applications (such as the wireless camera pill) have created new design challenges and frontiers requiring extensive research work. In such applications, it is often required to capture a large amount of data and process them in real time while the hardware is constrained to take very little physical space and to consume very little power. This is only possible using custom single-chip solutions integrating image sensor and hardware-friendly image compression algorithms. This paper proposes an adaptive quantization scheme based on boundary adaptation procedure followed by an online quadrant tree decomposition processing enabling low power and yet robust and compact image compression processor integrated together with a digital CMOS image sensor. The image sensor chip has been implemented using 0.35-mum CMOS technology and operates at 3.3 V. Simulation and experimental results show compression figures corresponding to 0.6-0.8 bit per pixel, while maintaining reasonable peak signal-to-noise ratio levels and very low operating power consumption. In addition, the proposed compression processor is expected to benefit significantly from higher resolution and Megapixels CMOS imaging technology