Parallel reduced area multipliers

As developed by Wallace and Dadda, a method for high-speed, parallel multiplication is to generate a matrix of partial products and then reduce the partial products to two numbers whose sum is equal to the final product. The resulting two numbers are then summed using a fast carry-propagate adder. This paper presents Reduced Area multipliers, which employ a modified reduction scheme that results in fewer components and less interconnect overhead than either Wallace or Dadda multipliers. This reduction scheme is especially useful for pipelined multipliers, because it minimizes the number of latches required in the reduction of the partial products. The reduction scheme can be applied to either unsigned (sign-magnitude) or two's complement numbers. Equations are given for determining the number of components and a method is presented for estimating the interconnect overhead for Wallace, Dadda, and Reduced Area multipliers. Area estimates indicate that for non-pipelined multipliers, the reduction in area achieved with Reduced Area multipliers ranges from 3.7 to 6.6 percent relative to Dadda multipliers, and from 3.8 to 8.4 percent relative to Wallace multipliers. For fully pipelined multipliers, the reduction in area ranges from 15.1 to 33.6 percent relative to Dadda multipliers, and from 2.9 to 9.0 percent relative to Wallace multipliers.     

Integrated circuits for channel coding in 3G cellular mobile wireless systems

Error control coding is a key element of any digital wireless communication system, minimizing the effects of noise and interference on the transmitted signal at the physical layer. In 3G mobile cellular wireless systems, error control coding must accommodate both voice and data users, whose requirements vary considerably in terms of latency, throughput, and the impact of errors on the user application. At the base station, dedicated hardware or readily reconfigurable components are needed to address the concurrent coding and decoding demands of a large number of users with different call parameters. In contrast, the encoder and decoder at the user equipment (UE) are dedicated to a single call setup which changes infrequently. In designing encoder and decoder solutions for 3G wireless systems, not only are the performance issues important, but also the costs. Cellular wireless infrastructure manufacturers need to reduce costs, maximize system reuse, and increase flexibility in order to compete in the market. Furthermore, future-proofing a network is a primary concern due to the high cost of deployment. For the UE, power consumption (battery life) and size are key constraints in addition to manufacturing costs. This article considers the 3G decoder design problem and, using case studies, describes two 3G decoder solutions using ASICs. The first device is targeted for base station deployment and is based on a unified architecture for convolutional and turbo decoding. The second device is a dedicated high-speed radix-4 logMAP turbo decoder targeted for UE, motivated by the requirements for high-speed downlink packet access. Both devices have been fabricated in 0.18 /spl mu/m CMOS technology, and while optimized for either base station or UE, may be used in both applications.     

An eight-user UMTS channel unit Processor for 3GPP base station applications

We present a multi-user W-CDMA baseband channel unit processor for cellular base station applications. The ASIC is compliant with the 3GPP/UMTS standard and exceeds 3GPP minimum requirements for high-speed data by 2.2-6.2 dB. It supports up to eight users simultaneously, with a mix of voice and data services and a maximum uplink data rate of 384 kb/s and maximum downlink data rate of 2 Mb/s. The ASIC implements preamble detection, searching, demodulation RAKE-finger processing, channel coding/decoding for voice and data services, and transmission functions. It is coupled to a DSP to form a complete channel element for eight users.     

A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-/spl mu/m CMOS

A channel decoder chip compliant with the 3GPP mobile wireless standard is described. It supports both data and voice calls simultaneously in a unified turbo/Viterbi decoder architecture. For voice services, the decoder can process over 128 voice channels encoded with rate 1/2 or 1/3, constraint length 9 convolutional codes. For data services, the turbo decoder is capable of processing any mix of rate 1/3, constraint length 4 turbo encoded data streams with an aggregate data rate of up to 2.5 Mb/s with 10 iterations per block (or 4.1 Mb/s with six iterations). The turbo decoder uses the logMAP algorithm with a programmable logsum correction table. It features an interleaver address processor that computes the 3GPP interleaver addresses for all block sizes enabling it to quickly switch context to support different data services for several users. The decoder also contains the 3GPP first channel de-interleaving function and a post-decoder bit error rate estimation unit. The chip is fabricated in a 0.18-/spl mu/m six-layer metal CMOS technology, has an active area of 9 mm/sup 2/, and has a peak clock frequency of 110.8 MHz at 1.8 V (nominal). The power consumption is 306 mW when turbo decoding a 2-Mb/s data stream with ten iterations per block and eight voice calls simultaneously.     

A VLSI 8 × 8 MIMO Near-ML Detector with Preprocessing

Multiple-input multiple-output (MIMO) systems are of significant interest due to their ability to increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits. A particularly difficult part of these systems is the detector, where the optimal maximum-likelihood solution is desirable, but cannot be directly implemented due to its exponential complexity. This paper addresses this challenge and presents a digital circuit design for an 8×8 MIMO detection problem. A key feature is the integrated channel preprocessing unit, which performs the channel decomposition functions that are either omitted or performed “off-line” in other designs. The proposed device achieves near maximum likelihood bit error rate results at 57.6 Mbps. Other novelties include a high speed sorting mechanism and power saving features.